Hi,

I've just finished 2 years graduate work as an Electrical Engineer working in the construction industry, I was designing circuits for electricians to install.

I really want to do something more cutting edge like FPGA or something else in electronics. I'm making around £40k a year.

Do you guys think I will need to step down significantly in salary in order to get the position?

Thanks

Let's say that one intends to get into intense FPGA design with mid-range FPGAs - models that mere mrotal can get his hands onto without selling his car in the process.

And perhaps run some SPICE etc simulations etc.

What PC should s/he look for:

• does high core count help ? Would 16-cored Ryzen 9950 be a killer for the job or maybe faster-clocked 9700X be better ? Or maybe one should look at Thereadripper, perhaps something wuth say 32 cores ?
• does extra L3 cache of X3D models help ?
• how about memory size and speed ? How much RAM should be enough even with multitasking - doing several things at once ?
• is GPU computing used to significant extent in these kind of jobs ? Is fa(s)t GPU essential and is there preferred brand (CUDA opr OpenCL etc) ?

Is all FPGAs Hard IPs "mapped from" pin configurations or ther's some specific HDL (VHDL, SysVerilog) lanugage extensions providing some features that are backed into fpga fabric?

My little bit of experience comes from Altera FPGAs

I am currently using FPGAs in an academic research project. I operate on a very low budget with my FPGAs being salvaged Kintex 7s on breakout boards from China. For the purposes of both cost and acoustics, I go for a cheap adhesive heatsink on the FPGA and a desk fan blowing on everything. In the worst case, I get around 75 °C die temperatures from the internal ADC which is under the specified maximum operating temperature of 85 °C.

From my experience previously using CPUs in a similar way, there is no issue running a loaded CPU 24/7 a few degrees from its thermal limits for years at a time. I always go for the lowest fan speeds I can get away with.

This point is not relevant to FPGAs, but the performance gains from better cooling via automatic frequency scaling on modern CPUs are never worth it for me. It's usually something like a 5% performance improvement at a dramatically increased cooler cost or cooler noise.

The Xilinx application notes seem overly conservative advising against adhesive heatsinks altogether. Hobbyists on the other hand tend to anthropomorphise their hardware and overcool it. Does anyone have interesting experiences or unconventional takes to share on this matter?

https://preview.redd.it/01oo5itr4iyd1.png?width=896&format=png&auto=webp&s=2c9ba7e56dcc7189f462946d5fb11526d480cc82

I have TerosHDL able to run my testbenches in Verilog, but I am seeing this error and wondering what it means and how to fix it. I am using ModelSim to run the simulations from TerosHDL.

Also, I have yosys installed from oss-cad-suite, but for some reason I cannot use the Schematic Viewer. When i hit the Schematic Viewer button all I see is:

2024-11-02 11:54:17.256 [info] Executing: C:\Windows\system32\cmd.exe  C:\Windows\system32\cmd.exe /d /s /c "C:/oss-cad-suite/start.bat yosys.exe -p "read_verilog -sv "c:\Users\Gabriel\Desktop\FPGA\test.v"; hierarchy -top and_gate; proc; write_json f-2024102-8464-afgknu.l4uw6; stat""
2024-11-02 11:54:17.352 [info] 
[OSS CAD Suite] C:\Users\Gabriel\AppData\Local\Temp>

Hii I have interview for digital design at cadence design system, plz provide any genuine tips for the preparation of online assessment or interview, which topic to study or so...

Is there a way to measure power on the ZCU104 without using the USB005 and XPE? Maybe an embedded C application or something?

To start, I am working on an SoC project with the Zynq 7020. Nearly every IP component I encounter uses some form of AXI interfacing, and while I understand its usefulness in the right context, I think its just plain overkill for many others.

In the project I am working in its been one of the biggest nuances to me and my partners. Can I just get a "ready" flag and a logic vector, or do we need this whole song and dance that requires three support components, memory maps, and more things to troubleshoot.

So my main question is really, once I start some chain of AXI masters and slaves, because some IP block requires it, is there ever any escape to simplicity again?

https://preview.redd.it/1pkb16roheyd1.png?width=998&format=png&auto=webp&s=586a2a22b03996fa8cbb5021272f743d220fc806

I try to run iverilog with a file list.
However, it doesn't work although I give the flist.txt every permission.
How can I fix that ?

There is a line in a verilog design as follows:

reg r_LED_1 = 1’b0;

What does 1’b0 do?

I'm using a Cyclone V 5CSEMA5F31C6, I want to fit a 32 bit RISC-V design that I made, but I'm using 48000/32000 ALMs. My design contains the ALU, the Program Counter, data memory, registers, and instruction memory.

I can see in the flow summary "Total block memory bits 0/4 million", I'm guessing that could be useful but I don't know how to use block memory in Quartus. Sorry if this is a stupid question.

I figured out how to generate some kind of file that connected ram adress and DQ pins to byte groups in data banks in groups.

I cant figure out how to find the pins for pcie.

Could someone help me with actually connecting pins of the memory and pcie slot with fpga pins in schematic and setting voltage levels?

I am used to dealing with microcontrollers and discrete components. I can handle the voltage regulators and decompiling caps. I can handle the length and impedence matching.

I just dont know how to draw the schematic. Pls help this fool

Also this is not my homework. I just like torturing myself.

So my country is really shit and increasingly dangerous as the time goes by so for the sake of my future and other people that will depend on me eventually i have been thinking about trying to go to US.

Robotics student right now,almost finished,planning to get masters in Digital systems while learning and doing projects on FPGA.In your experience,how willing are companies to sponsor someones visa,and how good would i have to be? Is it even possible for someone looking to get a foot into the industry rather then seniors and experienced engineers?

I am 23 right now so i have 2ish years to get my masters and learn as much as possible.

I ordered a mimas v2 Spartan 6 Fpga board . While searching for tutorials on how to program the device the only platform used is vivado ise which hasn't been updated and is only used on win10 . What resources or platforms do I use to program the device from here since vivado doesn't support Spartan 6 and started from the Spartan 7 series ???? Tl;Dr - need ide or platform to program Spartan 6 series fpga board that I ordered on win 11

Lets say i want to find leading one in N bit input in one cycle

Psuedo code for refernce

Always@ clk For(i=0;i<N;i=i+1) If (in[i]==1) begin

Out[i] <= 1'b1; Break;

End End

Break is not synthesizeable , I'm thinking to me some one hot based combo for input first and then use it

Any better way?

Yet another frustrated and exhausted post about the "wonders" of Vivado but I really need some help now. Basically, I'm trying to incorporate an IP from Xilinx (Floating Point IP) into my design by customizing it from the IP catalog. When I try to generate the output products out-of-context for this IP, Vivado keep the god forsaken error

[Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

I do not know where this comes from, my xdc file sets no properties, it just creates a clock, I can't find anywhere this set_property is used reasonably causing this error. For the first few times, I tried generating globally, but then after several attempts to get it work out-of-context, somehow switching back to global make synthesis to "Module not found"???

Someone please help me with this confusing problem. I have been searching all the internet for the past few days and still couldn't fix it. Thank you so much for your time and effort

I am only refering to sequential/synchronous logic.

What are some research papers or resources I should look at to give me some good ideas for a decent proposal. Any unique ways I can use an FPGA / Deep Learning Architectures to do data flagging, pattern recognition, time series analysis, ...etc! I hope I'm not being vague.

New to fpga design.

I have a working verilog code that will blink a led on the board.

Board is connected to my laptop using usb cable.

I want to understand in more detail about how my verilog code is put on the fpga.

“fpga tutorial” sites talk about rtl only.

I also read that there is sram onside fpga ic.

How is that used to put my code on the fpga ic.

Any webpage or yt video on this topic will be mighty helpful.

Thank you all.

I would like to sum for example 256 values of 16-bit. My current approach, in VHDL, is to create a function that sums the values in a loop, then add a bunch of register stages afterwards to allow backward retiming. I'm using Vivado and an UltraScale device.

Retiming seems to work, sometimes, but not always. I'm not sure whether the adder tree structure created this way is optimal. I have to investigate more. In the meantime, I wanted to ask what would be the best approach for this?

Hi everyone, I'm trying to get the following functionality written efficiently in SystemVerilog.

#include <stdio.h>
#include <stdlib.h>

#define NUM_ELEMENTS 8

int* sort_elements(int *data_array, char *valid_array, int *valid_elements) {
    int out_idx = 0;
    int *output_array = (int*)malloc(NUM_ELEMENTS*sizeof(int));
    for (int in_idx = 0; in_idx < NUM_ELEMENTS; in_idx++) {
        if (valid_array[in_idx] == 1) {
            output_array[out_idx++] = data_array[in_idx];
        }
    }
    *valid_elements = out_idx;
    return output_array;
}

void print_array(int* data_array) {
    printf("\n-------------------------------\n");
    for (int i = 0; i < NUM_ELEMENTS; i++) {
        printf("%0d  ", data_array[i]);
    }
    printf("\n");
}

int main() {
    char valid_array[NUM_ELEMENTS] = {0, 1, 1, 0, 1, 1, 0, 1};
    int data_array[NUM_ELEMENTS] = {1, 2, 3, 4, 5, 6, 7, 8};
    int num_valid_output_elements;
    int *output_array;

    output_array = sort_elements(data_array, valid_array, &num_valid_output_elements);
    printf("%0d elements are valid in the transfer", num_valid_output_elements);
    print_array(output_array);
    return 0;
}

Basically, given an 'N-element' array which has some valid and invalid elements, we want to output an N-bit array where all the valid elements are next to each other. We also have another N-bit input array like a strobe signal to specify which input element is valid and which isn't.

I want to find the most efficient solution which can be scaled based on parameterization (array size) and pipelined easily.

The few solutions I have in mind is to use a simple parallel bubble-sort algorithm which moves elements with the corresponding strobe signal set to one side, and invalid elements to another side. This architecture, although easy to code doesn't really scale well as the number of elements increase since it would take N stages for the full sort. One more solution is to use priority encoders to determine the index of the MSB and use that as the select signal to the multiplexers which then output a valid element.

Any thoughts and guidance would be appreciated here. Thanks.

Edit:

I've provided a basic stub file to show the IOs of the design:

module remover #(
    parameter NUM_ELEMENTS = 8,
    parameter ELEMENT_BITWIDTH = 4,

    localparam VALID_ELEMENTS_BITWIDTH = $clog2(NUM_ELEMENTS+1)
)(
    input logic clk,
    input logic areset_n,

    input logic [ELEMENT_BITWIDTH-1:0]  input_data [NUM_ELEMENTS-1:0],
    input logic [NUM_ELEMENTS-1:0]      input_strb,
    input logic                         input_valid,

    output logic [ELEMENT_BITWIDTH-1:0] output_data [NUM_ELEMENTS-1:0],
    output logic [VALID_ELEMENTS_BITWIDTH-1:0] output_num_valid_elements,
    output logic                        output_valid
);

// Example
// Input Transfer 1 input_data = [ 01, 02, 03, 04, 05, 06, 07, 08]      input_strb = [0 0 1 1 0 1 0 0] input_valid = 1
// Input Transfer 2 input_data = [ 12, 10, 11, 02, 14, 07, 15, 15]      input_strb = [0 0 0 0 0 0 1 1] input_valid = 1
// ...

// Output Transfer 1 output_data = [03 04 06 XX XX XX XX XX]            output_num_valid_elements = 3 output_valid = 1
// Output Transfer 2 output_data = [15 15 XX XX XX XX XX XX]            output_num_valid_elements = 2 output_valid = 1
// ...

endmodule

Any availability for IP Dev? How hard is it to get a job in IP development?

Any study material links?

I have been trying to build a petalinux project on my ubuntu machine only to find out that it does not work ...

I am a senior in undergrad and have been applying for full time positions in V&V, RTL, P&R, and timing roles this fall and haven't had much luck. Any advice or things I should change on here?

Hey everyone, hope you are doing well.

I've recently started to design a RV32 core.

It's going well, but until now, I've used very basic instruction and data memories :

/**
* DATA MEMORY
*/
wire [31:0] mem_read;

memory data_memory (
    // Memory inputs
    .clk(clk),
    .address(alu_result),
    .write_data(32'b0),
    .write_enable(1'b0),
    .rst_n(rst_n),

    // Memory outputs
    .read_data(mem_read)
);

It's fun and all but I also know this is not really a good way to go. these single cycle BRAM (it's bram right ?) are good for now but I plan on actually using the core for larger projects later on, AKA I need to use DDR memory availible on my FPGA.

But how ?

• Do I add a specific interface to my core in the I/Os ?
• How to handle multi-cycle reads ? (aka all of them since I don't plan on adding a cache for now)
• Do i need to declare my memory in a weird way to "invoke" it as DDR ?

I plan on using my core on Zynq SoC. Idk if it's important as well but my board is a Zybo Z7-20 but I guess this will be handled by Vivado when I'll work on the FPGA implementation ?

Looking forward to seeing your responses, have a good end of the week !

Edit : for simulation I use cocotb with icarus verilog (full open source haha)

I'm a newbie developing an undergraduate research on microarchitectures, but I'm having a really hard time building an ALU because of the various existing methods. I'm particularly stuck on the adder for a RISC-V build, because I'm really unsure of what to do with it and how to make it efficient with the least complex code possible. I'm using Quartus for this, writing code in SystemVerilog.

For now, I've looked at the look ahead carry, but it isn't appealing because of the complexity (I need to do something easier), yet the efficiency is something I really liked. I also started doing some combinational code, but for the size of the 32-bit ALU, it's turning a bit more extensive than I'd like.

I've learned from professors that an ALU should be combinational. Is it bad to make it into a sequential block? Is it less efficient? Thanks! I'm still learning all of this stuff.

A bit relevant data about the project

I'm working on a project that includes sampling a 10 MHz analogue signal at around 60 Msps on an ADS4222 (2 12 bit channels). The clock is generated using the ICE40UP5K's internal PLL (jitter doesn't matter that much for the chosen application) and an external TXCO. Data sampling on the FPGA is triggered using the ADS's output clock and stores data into a FIFO structure. All data readings following the write operation sequentially read the stored data. The SPI protocol is currently very simple to reduce the timing footprint. SPI write messages trigger the conversion, while SPI reads simply read the data one by one. First bit in the message specifies the operation.

This is the verilog source:

• core.v (connects all the components, instantiates the PLL core)
• ram.v (RAM and FIFO implementation)
• spi.v (async SPI core - counter is 5-bit)

The problem

When I sample the data, the FIFO counter counts fine (it stops sampling after the expected time), but no matter the source, whether it's a counter for debugging purposes or the actual ADC data, it doesn't appear to actually sample the correct data. Now if I set it to a constant, it seems to sample it into the FIFO just fine - when reading the data via SPI, I always get the same SPI bit stream as expected. This leads me to believe that there is something wrong with timing - whether it's on the read or write side of things since static data seems to work fine.

The 24 bit samples are interpreted as 2x12 signed integers. If I have it set up to read from a counter (should be sequential numbers) I get something like this:

If limited to 4 samples (read in pairs, so data appears to be changing mid readout?):

-1868,-1869,176,52,-1866,-1867,176,54

If I use larger sample buffers (let's say the full length of 4096) I get what appears to be random samples filled with a bunch of zeroes:

https://preview.redd.it/knlm9ro2m4yd1.png?width=1900&format=png&auto=webp&s=c7909c8d6d0bf23ce12f2ca7c06a71ecf20e068b

What I confirmed is working

• The async SPI core is working: if I load registry data and read it on the connected MCU, I get correct readings.
• Parallel data lines are wired correctly: sampling the current reading in a registry at the time a new SPI message starts successfully sends a sample pair via SPI directly - when I sample a sine wave I get the corresponding bathtub histogram
• The ADS conversion done clock is wired correctly: If I time the "busy" line on an oscilloscope I get roughly the time of 4096 clock cycles
• The configuration works correctly when simulated in ModelSim, so I'm assuming it's something with timing (simulated with data depth of 4 measurements):

A simulated sampling operation:

https://preview.redd.it/q8p27kk5m4yd1.png?width=1234&format=png&auto=webp&s=b9b2df9ad41c560c2baad8688a1e0cba2fb1d616

A simulated readout operation via SPI:

https://preview.redd.it/sbtmf997m4yd1.png?width=1282&format=png&auto=webp&s=97d1b3bb8d89e11bac364b73d31e55fccc5dca03

The sample timing should also be correct, at least in theory, according to the TI ADS42xx family's datasheet (figure 7-1):

https://preview.redd.it/gnxu45lem4yd1.png?width=424&format=png&auto=webp&s=6c5083f2afdb8285fdf54424d980aa249dfc6001

• I'm not near the EBR ram max speed either as per the ICE40 family datasheet:

https://preview.redd.it/2wlgsghdm4yd1.png?width=841&format=png&auto=webp&s=746a635d5d831e7114cfe2158199a2bbeafe493f

I tried playing around with this structure a lot in the past few weeks and had no luck, so I'm wondering if anyone had similar issues. I'm new to FPGAs in general so I'm sure it could be that I missed something completely generic and stupid, so I decided to ask in this community if anyone is willing to share their experience.

Thank you in advance!