Event Date / Time: May 1 @ 2PM ET.

Register: (Reddit doesn't like Zoom links, so register from our website) https://bltinc.com/xilinx-training/blt-webinar-series/

https://preview.redd.it/ql9i3apmwgwc1.jpg?width=4167&format=pjpg&auto=webp&s=084bcee44ff245a46a7eabe30b46da7a0f222398

In this webinar, learn how to get started programming the Versal AI Engines using the Vitis IDE. This session provides a thorough introduction to the Vitis IDE for AIE development, and how to use the AI Engine Simulators to quickly develop and test your AI Engine designs. This webinar includes a live demonstration and Q&A.

BLT Engineers have successfully deployed designs to Versal devices for Clients. Learn from the experts.

BLT, an AMD Authorized Training Provider and Premier Partner, presents this webinar. www.bltinc.com

I have an interview for a design verification intern role today, but I have no experience as a verification engineer. Although I do have some knowledge about RTL design. What do you guys think I should prepare for this interview apart from basic digital electronics.

Hi, i am a year 3 computer engineering student who is going to do an internship as an Embedded Software Engineer.

However, I wanted to do something related to FPGAs but couldn’t get FPGA internships.

I would like to know if what I learn during the next 3-4 months as an embedded software engineer will help me getting strong in the field of digital design/FPGA? I’m guessing those are 2 different fields.

Can someone advise me on this?

I am also planning to take some courses on digital design to further strengthen my knowledge so that when I graduate next year i can stand a chance in applying for FPGA jobs.

In Bitcoin, the aim is to test as many as small inputs as possible. This means the best is to have several compute sha256 units.

But many times, increasing the throughput of 1 sha256 unit leads to take more room : for example, let’s say a pipelined design using some carryless adders takes 855 ᴀʟᴜᴛs on a Aria 2 gx ꜰᴘɢᴀ yielding a 1756.58 Mbps throughput, that same design using an unfolding factor 2 uses 1345 ᴀʟᴜᴛs and yields a 3621.07Mbps which means using 36% more space for a 51% performance improvement.
But an unfolding factor 4 uses 2064 ᴀʟᴜᴛs on the same ꜰᴘɢᴀ for a 4196.30 Mbps throughout, this means using 35% more space for a 14% throughput increase which can be Ok if hashing a large object, but isn’t for Bitcoin mining since it shrinks the number of units more than it worth to increase the per sha256 unit throughput.

I’m noticing the latest open source verilog designs for Bitcoin look to be purely iterative without even pipelining, but it’s been 10 years now that ꜰᴘɢᴀ mining for Bitcoin isn’t relevant and at that time it was pretty still amateur.

So while the mining algorithm I target differs from Bitcoin a little (input is always 256bits and is sha256 1 time instead of twice), I’ve no idea how Bitmain achieve computing 130Ghash/s per Watts since the designs aren’t open‑source. So what’s the best room/throughput trade‐off when designing a sha256 unit for mining that targets high‑end ꜰᴘɢᴀ cooled in the fluorinert ?

I have noticed that all the people that have worked with FPGA in the past are saying that FPGA is super expensive technology but I have noticed a trend in past few years (3-4 years) where prices are getting lower and lower. Nowadays a lot of students can afford some basics FPGA and learn some intro stuff with them or even make cool projects. Why FPGA suddenly became less expensive in past few years?

I'm a beginner in FPGA design and have chosen to do a project that involves an FPGA.

The project is to use an FPGA for image processing purposes, to detect when a 3d print is failing. It would essentially edge detect the ongoing print and compare it to what the print should look like.

This image processing led me to find a kit called Kria KV260 Vision AI starter Kit as it is designed for these kinds of tasks and has easy setup for the cameras. My question is can still write my own HDL for edge detection and load it onto the FPGA or is this mainly used for tweaking pre-built AI models?

Let me know your thoughts on this kit or if there is another board I should look at.

This one was attractive for the following:

-under $300

-Can handle video

-easy camera set up

-could implement ai for more robust error detection later on (although not vital to the project)

https://www.amd.com/en/products/system-on-modules/kria/k26/kv260-vision-starter-kit.html?utm_campaign=kv260&utm_medium=redirect&utm_source=301

The issue I have is that I need to synchronise two measuring devices (both with FPGAs) so that they start measuring at the exact same moment as possible.

As the device works alone it generates an output signal which starts the measurement and which is repeated cyclically until the measurement stops. I have the option of outputting this signal to an additional pin from one device (let's call it Master) and inputting it to an additional pin to the other (Slave).

1. I am wondering if it makes sense to simply take the input signal in the Slave and output this signal from the Slave as its own measurement control signal. I would then have to somehow delay the output from the Master to the actual measurement so as to compensate for the delay due to the buffering of the signal in the Slave.

2. However, would it then be better to treat it as an asynchronous input in the Slave and route it through the two registers and only then output?

Perhaps something more reasonable can be done?

I’m a new Firmware engineer at a company working with Xilinx FPGAs. Only do PS, no PL. hearing about the problems my counterparts on the FPGA deal with doesn’t sound like it passes the smell check. I understand the builds take forever, but they seem completely unstable. A working build can be recompiled and will stop working. Fixing one tiny issue in one area often results in something completely unrelated breaking. They’ve complained about not having space, and that any more tools for debugging is going to complicate the design even more. It just seems like a house of cards. Are all FPGAs projects really like this?

Hi,

I have an issue that a reset value is being assigned to zero instead of the value described in the reset statement. The reset is functional and verified in simulation using Verilator. However, in hardware, the value is observed to be zero using the ILA. The vivado version is 2021.2.

There were two versions tested in hardware using the ILA. They all have zeros as the reset value.

Version 1

`default_nettype none

module # (
   ...
   parameter integer DEPTH = 16,
   ...
) (
   ...
   output logic [$clog2(DEPTH):0] empty_count,
   ...
)

   always_ff @(posedge clk) begin
      if (rst) begin
         empty_count <= DEPTH[$clog2(DEPTH):0];
      end
   end

endmodule

Version 2

`default_nettype none

module # (
   ...
   parameter DEPTH = 16,
   ...
) (
   ...
   output logic [$clog2(DEPTH):0] empty_count,
   ...
)

   always_ff @(posedge clk) begin
      if (rst) begin
         empty_count <= DEPTH;
      end
   end

endmodule

For reference, the module is instantiated with a DEPTH of 256. The ILA shows the width of empty_count as 9 bits, [8:0], which is sufficient storage to hold the value 256. SystemVerilog treats the value of DEPTH as unsigned, therefore it is not a truncation issue.

Any tips or suggestions would be appreciated.

Thank you.

Hello everyone, I am Junior currently taking DSD class, and my final project is due May 9th and I was wondering what to do. This is my first class using FPGA(Nexys A7), and we have done labs ranging from simple 7 display segments, to using calculator to do addition and subtraction to using vga to display pong. So I was curious what would be an appropriate cool project. I want to do something that is "resume worthy" but at the same time I don't want to more than I can handle. Thanks for any input in advance.

I am trying to interface ov2640 camera through SCCB. I am not using the AXI IIC IP core and am instead writing the driver myself (i2c implementation with sda and scl wires, 8 bits followed by a dont care) .

I understand that the programming sequence for setup of registers is:

start condition (1bit),

sccb address (0x60 for write, 0x61 for read) ,

register address,

data(8bits +1bit dont care),

end condition (1bit).

Do I need to send the SCCB Slave ID or Product ID first before specifying the register address?

page 22 ov2640 datasheet

page 20 ov2640 datasheet

I would greatly appreciate it if I could get a list of the sequence!

Note: I am using MicroBlaze with micro-controller preset if that changes anything.

Can a part which lists 1333 or 1066 MTs as available be run at an arbitrary speed as long as the timing parameters are followed? E.g. at 1200 or 1000 MTs? I cannot just google this due to PC gamers.

Hi, I am new to the scene of FPGAs, and I have a project that needs a time-domain convolution of an audio signal (1Hz-20kHz). I have experience using microcontrollers, and I implemented a real-time, time-domain convolution on a Teensy 4.1 (600MHz) dev board, which convoluted a time-domain signal with a kernel (length=2000 points). Only problem is that I need an input-output latency of <1ms, and the Teensy 4.1 setup had an input-output latency of ~10ms after I optimized all I could.

Does anyone know of an example of someone implementing a real-time convolution on a FPGA? I think FPGAs are well equipped to perform the convolution, should be a (comparatively) simple problem. But does anyone have any good places to start? - I can't be the first one to do a real-time convolution on this type of hardware.

I was looking for a way to increase performance, which is when I came across FPGAs. After doing some research, it is something I want learn more about, they seem very powerful for DSP applications. I don't mind going down rabbit holes (phd student), and I have plenty of time to learn.

Thanks for the recommendations!

Hi everyone,

I want to use the DAC/ADC units of Zynq UltraScale+ RFSoC in my project. I have found the attached schematic to connect ADC/DAC to the PS memory to read/write data. However, I can't estimate what the maximum DMA bandwidth or maximum bandwidth of HP0 and HP1 ports are. Any hints would be appreciated.

Thank you!

https://preview.redd.it/7uolcw9anawc1.png?width=1138&format=png&auto=webp&s=4701709bdec5e29050cb1dac2e043479296f38f9

Hey y'all, long story short I'm trying to use Ring Oscillators to create a power monitor on a Xilinx board. I am using vivado for the design but whenever I try to synthesize it I get the error shown in the picture below. Additionally there is no board usage when I open the synthesized design, is there a way to force Vivado to let me implement all these ring oscillator circuits?

There are frequent requests for recommendations for a project idea for FPGAs. Rather, let's make a list of interesting open-source FPGA projects that welcome new contributors. I believe that solving real-world problems and collaborating with other developers will give everyone a lot of useful experience. Do you know such projects?

I have access to a zedboard and a zynqmp ultrascale. What are some intermediate to advanced projects that I can do to improve my FPGA/dsp skills and that would improve my resume as well. Thanks

Hi everyone. I'm the FPGA recruiter who reached out some time back inquiring about primary regions in the US where FPGA talent tends to be concentrated. I was helping a US-based company seeking to transition some of its FPGA engineering talent from Europe to the US due to government contract requirements. Your feedback was immensely valuable on that post (thank you.)

Fast forward to today, the company has decided to embrace fully remote US based roles (thank goodness.) Their priority is to hire an experienced technical lead. The title currently is Systems Software Engineer with a background in Electrical Engineering and strong understanding of FPGAs. Engineers that have worked on test measurement equipment (such as equipment from National Instruments, Keysight, Tektronix) would be ideal. Backgrounds in RF, defense, aerospace are also ideal.

If anyone would like to hear more, feel free to reach out to me through messaging (yes, I will promptly respond.) I'm also always open to general conversations about FPGA jobs/roles. I worked at FLIR Systems for 8 years and was the lead recruiter for their FPGA talent, it's been my speciality. Thank you!

Hello All,

How do I get the bit stream address for the DFX controller? and for the size should I use .bin or .bit size?

​

https://preview.redd.it/eoyt1ksma9wc1.png?width=1389&format=png&auto=webp&s=13f929debef3eac8de592d399c56fc07a0b31717

Best regards,
Jasmeet03

Hey Redditos! 🎉 I'm learning VHDL and I need really your expertise! 🙏

Currently, I'm working on a small project aimed at designing VHDL code to display a 4-bit value on LEDs that can be both incremented and decremented using a rotary encoder. My idea is to implement an up/down counter, but I'm struggling with integrating the rotary encoder signals into the code.From what I understand, the rotary encoder signals can help determine the direction based on the position of the pulses. then, we can count the pulses in each direction to adjust the value accordingly.

Here's my initial VHDL draft:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity rotary_counter is

port(

clk, UD: in std_logic;

leds: out std_logic_vector (3 downto 0) );

end rotary_counter;

architecture behav of rotary_counter is

signal counter: std_logic_vector (3 downto 0);

begin

process (clk)

begin

if (clk'event and clk='0') then

-- mod-16 up counter

if (UD='1') then

counter <= counter+'1';

-- mod-16 down counter

elsif (UD='0') then

counter <= counter-'1';

end if;

end if;

end process;

leds <= counter;

end architecture;

Could anyone help me integrate the rotary encoder signals with this code? I'm a bit lost here. Thanks a bunch in advance! 🙌"

https://preview.redd.it/pexp6g1549wc1.png?width=627&format=png&auto=webp&s=855faeb8670d365eeadba764de421da13b3d967f

I encrypted an IP in Vivado. Can you help me decrypt it with TCL syntax or other any steps?

We have a research study about denoising biomedical signals through hardware implementation using FPGA. A model-based design of the denoising algorithm in Simulink was converted into Verilog HDL code using HDL Coder in Simulink. The Verilog HDL Code was synthesized and being programmed using FPGA Cyclone V DE10-Standard Board. The input and output pins of the code consists of 16 pins. In the FPGA, we utilized the GPIO or General Purpose Input and Output Pins to program the Verilog HDL code using Pin Planner in Intel Quartus II. We want to test whether the programmed FPGA in denoising signal is working. The test setup is the 16 bit signal from the Simulink will send its data using the NI DAQ USB 6353 to its digital output. The digital output of NI DAQ is connected to the 16 bit inputs assigned in the FPGA. Lastly, the digital output pins of the FPGA is connected to the input pins of the NI DAQ so that the results of the FPGA would reflect in the simulation in Simulink. We found that the FPGA has 3.3 TTL output logic in the digital I/O pins of the FPGA. And upon simulation, we cannot get the expected results that the input biomedical signals should be denoised using FPGA.

Is it right that the Digital I/O Logic level on NI DAQ USB 6353 is 5V TTL? If yes, is it right to connect a 3.3 V TTL logic of the FPGA into a 5V TTL of the NI DAQ? Is it required that the TTL logic of both device should be matched in order to yield an expected results? If yes, what steps should we in order to change the TTL voltage level of NI DAQ USB 6353 into 3.3V TTL?

Thank you very much.

Hi folks!

I'm getting some combinatorial loop warnings from Xilinx tools. The warnings are cryptic so naturally I want to see if I can get something nicer from Verilator. But Verilator doesn't report any combinatorial loop at all. So I guess this is a false negative of Verilator? How often do you see this (I'm quite new to FPGA RTL design)?

Also, do you have tips on debugging combinatorial loops? Thanks!

Hi guys,

I wanted to upgrade the Quartus version of my design from 17.1 Std to 21.3 Pro. The design is compiled perfectly on Quartus 17.1 on Ubuntu 20.04. I copied the old design's Quartus folder which included all the files needed for the project on Quartus Std 17.1 and created a new folder (with a different name) with Quartus Pro 21.3 in order to get the IP upgrade automatically.

After upgrading the IP blocks, I wanted to generate HDL and then synthesize the design so that I can test it on the new hardware, but I'm getting errors from the custom IP components that are bought from another company. When I open the project on 17.1 Std, I can see the ports of the bought IP connected to the other blocks in the design, but when I open the Platform Designer on 21.3 Pro, I do not see the generics and the ports of the custom components. I believe the reason of that is because of the errors when I try generating HDL. The errors (same type but for different entities, for simplicity I share only one of them) I see are given below:

Error: max_SOM01_ntl_clk_clock_0: set_parameter_property: Parameter property type cannot be modified after adding the parameter. Please set property type during add_parameter.

The IP itself is already added to the QSYS file (which was copied from the older project as well). I do see one generic for some of these custom IP blocks from all of their generics, but no signals at all.

I'm not sure what is wrong/missing here, any help from you guys would be much appreciated!

Recently I saw pretty timing diagrams in documentation. Please see this project for example:

https://srimanthtenneti.medium.com/my-approach-to-designing-an-ai-accelerator-9d8d2af1f7f9

I thought this was TimingAnalyzer? But latest download links are broken or plagued with viruses. Did I miss another great tool for timing diagrams?

https://web-site.readthedocs.io/en/latest/features.html