Hi all, welcome back to me trying to make my design work in vivado ep5.

Recently succeeded in implementing a design but the timing keeps failing :

Example

The thing is I've lowed the clock from 40 MHz down to 10 and the WNS is always about the same. The problem is even worst since I added a whole bunch of ILAs, do you think it's related ?

Here is the design :

https://preview.redd.it/qvhoyffr1p4e1.png?width=1256&format=png&auto=webp&s=169dc43b975c25d59b9c5488b50e9d1641f27d1d

Do you have tips to "force" the clock in a state where it means timing ? Note : I modify clock frequency in the clk_wizard IP.

Have a good rest of your day.

NB : Here is the worst path :

Worst case path

I don't really know if I'm right but looks like "inter-clock" and the fact that it is *within* the FPGA hint me towards CDC issue. oh men... I think I'll go to sleep.

I'd like to synchronize signals like "singlepulse" or "swacc" to a ~10x faster clock domain. It would be great to have this clock spec'ed in the .rdl file, then auto generate the synchronizer flops.

1. Does support like this exist (I couldn't find anything in the peakrdl documentation).

2. Can peakrdl-regblock be extended to provide this functionality.

Help is greatly appreciated ;)

Following on from u/FaithlessnessFull136 effort (using "wait until rising_edge(clk);" in synthesisable code), here is blinking an LED without any processes at all.

Behold the wonder that is the clocked concurrent statement!

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity blink is
    Port ( clk : in  STD_LOGIC;
           led : out STD_LOGIC);
end blink;

architecture Behavioral of blink is
    signal count : unsigned(24 downto 0) := (others=>'0');
begin
    count <= count + 1                  when rising_edge(clk);
    led <= std_logic(count(count'high)) when rising_edge(clk);
end Behavioral;

Myself, hardware engineer I have partnered with a mathematics Ph.D and we want to implement a Machine Learning algorithm that is super fast and efficient, on FPGAs, we have the code running in C and Java at the moment as working examples.

Neither of us have experience on FPGAs and it is essential for this project. This is a high risk - high reward project.

If developing FPGA systems is your passion and you do not seek an immediate salary, have enough experience to develop complex computing solutions, get in touch with us!

Hi everyone,

I'm on the lookout for an ALTERA MAX EPM7160STI100-10N FPGA with the following additional markings:

• WCDC241831A
• S833AV46
• 3A1QABCON

I've tried a few online electronics suppliers but haven't had any luck finding this specific part. Does anyone know of reliable sources, marketplaces, or suppliers where I could track one down?

I appreciate any help or advice!

Thanks in advance!

https://preview.redd.it/88136foq5o4e1.jpg?width=336&format=pjpg&auto=webp&s=5c0199a125b402939d92cdbdb8f61778010ab221

I'm trying to open the TCL shell from the command line I run inside my project folder and I type: Vivado -mode tcl.

However it gives me an error and it says it can't find Vivado. I'm sure that it's a problem related to the fact I am calling it from a folder I'm not supposed to call it from.

How can I fix this?

Hi, I am an electronics engineer, just finished my MSc and I have a job in a company where I do some FPGA design but not as much as I would like (I mostly get a lot more Linux bash scripting than FPGA design tasks). Does anybody need some volunteer for FPGA projects of any kind?

I just want to learn and gain more experience in FPGA design and using preferably AMD Xilinx Vivado with VHDL which I am more familiar with (I am willing to learn also Verilog if necessary).

Does this scope plot of a SPI transaction look okay? I can't tell if these edges should look sharper, especially the CLK. Blue = CLK, pink = CS, green = MOSI. The CLK is running at 10MHz, and this was taken with a 200MHz oscilloscope, using 200MHz probes. The oscilloscope model is Siglent SDS824X HD. The signals are being driven from GPIO pins in bank 34 of an Artix7 FPGA, if that matters. Bank voltage is 2.5V and the IOSTANDARD is set to LVCMOS25.

The SPI slave is not responding, so I am trying to determine if it's dead. My question though, is primarily about the oscilloscope capture, and weather I should expect "cleaner" traces with sharper edges? I have the probe coupling on DC, BW limit at "full" and probe multiplier at 1x. I have tried playing around with these settings but haven't been able to get a cleaner plot.

https://preview.redd.it/5qdayz5l4n4e1.png?width=1024&format=png&auto=webp&s=cc31a91d0eb1b1f087845da9d3b7b228db0a1253

https://preview.redd.it/kek60ykbsn4e1.png?width=1938&format=png&auto=webp&s=ef4d5c81ce4e33dbce95fbf581322f914cb8868a

Edit: I attached the timing diagram from the SPI slave device for anyone interested

I am trying to get data from pl to ps with a DMA. I build the design according https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1027702787/Linux+DMA+From+User+Space+2.0 but I can't get it to work. I also tried this with modifications for the zuboard1cg what I am using. https://www.hackster.io/whitney-knitter/introduction-to-using-axi-dma-in-embedded-linux-5264ec

I am using 2023.2 but also tried it on 2022.2 and 2021.2.

At this point I've tried many things:

Dma proxy added in device-tree

Adjusted buffer sizes

Turned off SG

Hardware is built like the prototype.

Code is implemented, build an application and module

Added the dma proxy in the device-tree.

Built the petalinux project with enabling dma engine.

Enabling the module with insmod and trying the internal test. Test failes says something about buffer length not equal.

Running the dma_proxy_test application gives me the error that the channels are not enabled when I clearly can view them in /dev.

I tried it without cache-coherency and with it.

https://preview.redd.it/bhqqd1w51p4e1.png?width=827&format=png&auto=webp&s=0cca84c56e58535b7ae91f95e8464d46d3dc1b94

I have been applying for Fpga jobs but have not been getting any callbacks I have software, non work Fpga experience and 4 years of experience at a top ASIC company for design and verification

What is the best way to get through recruiters to get an interview as the skills are transferrable?

Hi all,

I recently purchased the Genesys ZU: Zynq UltraScale+ MPSoC Development Board with the intention of building a prototype for a multispectral imaging system. The goal is to connect six cameras simultaneously to capture data across multiple spectral bands. However, after reviewing documentation and forum discussions, I’ve discovered some limitations with my current setup:

Current Findings:
The Genesys ZU has two MIPI CSI-2 ports, which allow direct connection to two cameras (like the Pcam 5C).

The FMC Pcam Adapter, which I hoped would let me connect four additional cameras, has limited compatibility with the Genesys ZU. According to Digilent, only one out of four cameras can be reliably mapped, allowing for a total of three cameras (2 via MIPI + 1 via FMC).

What I Want to Do:
My system needs to support 6 cameras simultaneously, with the FPGA processing all camera data in real-time for alignment and spectral analysis.

I want to prototype a setup that allows for testing this multi-camera system before scaling up.

Challenges:
The Genesys ZU doesn’t seem suitable for 6 cameras out of the box. I’m considering alternatives, like designing a custom carrier board with multiple MIPI CSI-2 ports or switching to a different FPGA development board.

I’m also exploring options like MIPI aggregators or distributed FPGA setups, but I’m unsure how to proceed with hardware design and firmware development.

What I Need Help With:
Suggestions for FPGA Boards: Are there other FPGAs or development boards that can handle 6+ cameras simultaneously?

Custom Carrier Board Guidance: If I stick with the Genesys ZU, how can I design a carrier board to support more MIPI cameras? Any examples or tutorials would be greatly appreciated.

MIPI Multiplexing: Are there any ICs or solutions (e.g., Lattice CrossLink) that would help aggregate multiple MIPI streams to fit within my FPGA’s limitations?

Alternative Approaches: Is there a better way to prototype a 6-camera system for multispectral imaging without completely starting over?

Why I’m Doing This:
This project is for a multispectral imaging system, where I need to collect synchronized data from 6 cameras to analyze spectral bands in real-time. It’s a mix of hardware and FPGA processing challenges.

I am trying to design a debouncer for a simple button and led to combine with a university assignment but am getting lots of timing errors when running implementation in Vivado.

I have not dealt with timing issues before so honestly have no idea where to start with this. I would appreciate if anyone could explain what it is that I am seeing and if you have any pointers for what I could do (or resources to read up on to help me understand).

You can see my VHDL code and report methodology below.

VHDL for Button:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity btn is
  Port (btn : in std_logic;
        clk : in std_logic;
        led : out std_logic);
end btn;

architecture Behavioral of btn is
    
    component debounce is
    Port (  btn_in     : in std_logic;
            clk        : in std_logic;
            btn_out    : out std_logic);
    end component;
        
begin

    btn_1 : debounce port map(btn, clk, led);

end Behavioral;

VHDL for Debouncer:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity debounce is
  Port ( btn_in     : in std_logic;
         clk        : in std_logic;
         btn_out    : out std_logic);
end debounce;

architecture Behavioral of debounce is
    constant delay  : natural := 2**20;
    signal counter  : integer range 0 to delay := 0;
    
    signal btnd0    : std_logic;
    signal btnd1    : std_logic;

begin

clk_domain_crossing:
    process(clk)
        begin
            if (rising_edge(clk)) then
                btnd0 <= btn_in;
                btnd1 <= btnd0;
            end if;
    end process;

debounce_counter:
    process (clk)
        begin
            if rising_edge(clk) then
                btn_out <= '0';
                if (btnd1 = '0') then
                    counter <= 0;
                elsif (counter < delay) then
                    counter <= counter + 1;
                end if;
                if (counter = (delay - 1)) then
                    btn_out <= '1';
                end if;
            end if;
    end process;
end Behavioral;

Report Methodology

Table of Contents
-----------------

1. REPORT SUMMARY
2. REPORT DETAILS
3. REPORT SUMMARY ----------------- Netlist: netlist Floorplan: checkpoint_btn Design limits: <entire design considered> Max violations: <unlimited> Violations found: 24 +-----------+------------------+-----------------------------+------------+ | Rule | Severity | Description | Violations | +-----------+------------------+-----------------------------+------------+ | TIMING-17 | Critical Warning | Non-clocked sequential cell | 24 | +-----------+------------------+-----------------------------+------------+
4. REPORT DETAILS ----------------- TIMING-17#1 Critical Warning Non-clocked sequential cell The clock pin btn_1/btn_out_reg/C is not reached by a timing clock Related violations: <none>

TIMING-17#2 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/btnd0_reg/C is not reached by a timing clock
Related violations: <none>

TIMING-17#3 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/btnd1_reg/C is not reached by a timing clock
Related violations: <none>

TIMING-17#4 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/counter_reg[0]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#5 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/counter_reg[10]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#6 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/counter_reg[11]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#7 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/counter_reg[12]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#8 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/counter_reg[13]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#9 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/counter_reg[14]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#10 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/counter_reg[15]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#11 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/counter_reg[16]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#12 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/counter_reg[17]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#13 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/counter_reg[18]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#14 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/counter_reg[19]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#15 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/counter_reg[1]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#16 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/counter_reg[20]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#17 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/counter_reg[2]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#18 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/counter_reg[3]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#19 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/counter_reg[4]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#20 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/counter_reg[5]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#21 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/counter_reg[6]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#22 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/counter_reg[7]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#23 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/counter_reg[8]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#24 Critical Warning
Non-clocked sequential cell
The clock pin btn_1/counter_reg[9]/C is not reached by a timing clock
Related violations: <none>

Hi. Does anyone know where I can get practice interview questions and interview prep for fpga jobs (entry level). Thanks

Hi,

My relation to HDL has been mainly on Verilog, has been more on designing and generating testbenches, check the circuit behaves as expected, but never place close attention to Timing on Place and Route.

I have seen some interesting Junior level positions but clearly state that Place and Route and Timing Analyisis experience is required.

1. What kind of knowledge is expected from a Junior level hardware designer on Timng, P&R?

2. How can I get that experience, what kind of projects can I do?

3. Do I need an FPGA development board or can the be done with some simulation tools? Do I need commercial tools or do Open Source tools work for this also?

Thanks.

Hi everyone,

I'm on the lookout for an ALTERA MAX EPM7160STI100-10N FPGA with the following additional markings:

• WCDC241831A
• S833AV46
• 3A1QABCON

I've tried a few online electronics suppliers but haven't had any luck finding this specific part. Does anyone know of reliable sources, marketplaces, or suppliers where I could track one down?

I appreciate any help or advice!

Thanks in advance!

https://preview.redd.it/8ql074ca1o4e1.jpg?width=336&format=pjpg&auto=webp&s=161133c0227d1aeeeb5c49514b26da414cc9f9e7

Hey everyone, I had a ruthless experience with a company in this industry. I just thought to tell my story so I could prevent more people from being hurt by this company or in similar scenarios.

I passed the interviews and got an informal offer through email and decided to accept the offer, At that point, I had 2 months left until my visa expiry. I waited weeks until I got the contract and was asked by HR if I had any questions about the contract. I had a few questions about the process around work visas which I listed and emailed. I was waiting for the response until the hiring manager, decided to withdraw the offer when only 20 days were left before my visa expiry. The company and this person did not care to elaborate any further about the reason for their action and any further communication from my side to this company was left unanswered. Just like that they decided to play with the life of an immigrant in foreign soil who had put trust in them in the most crucial part of his life. Decide for yourself about the character and moral code of these folks and whether you want to put any trust in these people in similar situations.

Hi there,

I'm currently a bit lost on a problem, as I am a total noob, but maybe someone has done the same already. I have an audio implementation with audio data arriving in my FPGA on a zynq 7010.

Now I want a way to get the audio feed into the Buildroot Linux running on the ARM side so I can use it as e.g. an ALSA device. How would I tackle this problem? Is there anything I can use? What formats would be suitable? Any drivers already out there?

Hi everyone,

I'm looking for guidance on implementing an I²C passthrough between a pair of pins on an FPGA. The I²C pair connected to a slave device is routed under the SoM module, and I need to update some registers.

Is there a way to connect an I²C Master (such as a logic analyzer) to the FPGA's GPIO pins and pass the signals through to the slave device's pins?

Any advice, examples, or resources would be greatly appreciated!

Hello everyone, my previous board was DE-10 Lite (University Loaner) and I enjoyed doing VHDL on it and have designed a processor from scratch, and have also uploaded Nios II and an RTOS and controlled stepper motors and such with it. I was hoping to dive deeper into VHDL, SystemVerilog and UVM for now and in the future, try out embedded systems development so I am wondering if the PYNQ Z2 would be the right choice for me? Thank you for your time

I’m asking this just to plan ahead for my career. If I get a FPGA role at a HFT firm after getting my master degree, since they pay pretty well even for a new grad, and after 1 or 2 years decide to transition to a more traditional FPGA role like in chipdev/SerDes/DSP/emulation etc. How difficult would that be? It would probably depend on how good someone is with their skillset but I just want to know how many people usually pull it off?

Hi,

I want to connect a MIPI DSI screen to a Digilent Arty Z7 board. The board has no native MIPI DSI connector, but two standard Pmod ports and many GPIOs.

Is it possible to somehow connect a MIPI screen to this board and use the MIPI DSI Tx Ip to drive it? I haven’t found any Pmod MIPI adapters or MIPI to GPIO boards.

How would you go about that?

I bought an Zybo board from Digilent and I can't access getting-started guides and tutorials

because the Digilent reference site is down while the store website and the forum work fine

and I don't know if I can get these tutorials from anywhere else

but anyway, I wanted to make sure whether the problem on my end or theirs

UPDATE: The website is back online now

I'm trying to design an FPGA development board (around a SOM) that is going to use 2 cameras as once.

Right now my choice is the RPi Cam 3, my concern is whether or not I can run the libraries. The cameras use libcamera/rpicam-apps libraries which run on ARM so I don't see why not (but I'm not certain). Also what version of Linux can the Cortex A9 handle? Could it only handle a very old version that the libraries don't support?

Also goofy question, isn't the A9 a little too slow for an FPGA (yes I know Zynq 7000 is old) especially when it seems that everything is around/goes through the PS (for example, the PS always boots first)? I was under the impression that the PL is supplementary to the PS not the other way around

https://preview.redd.it/3qzh01bis84e1.png?width=728&format=png&auto=webp&s=4a93edd1f9270ef86998cb2e52bf19042ec7d2ef

so i'm trying the output of the XADC to the 16 LED's but I keep getting a weird overflow problem. I can confirm that the data ranges from 0x000 to 0xFFF but after my potentiometer reaches the halfway point, the LED's start from the beginning...

What could be the problem here?

Hello,

I have a school completion coming up, we are supposed to make a CPU that can do branches, to be ranked high based on performance I am advised that a superscale CPU is the best approach is there any useful diagram that could help in designing one? or any resource I appreciate it.

Thanks

I want to but an FPGA with an ethernet interface whose pins I can access from the fabric. I want to first start with implementing ARP, then setup a connection between my PC and the board using an ethernet cable over a network switch. Going from there, I want to then implement UDP, then (ambitious) 1G Ethernet. Basically I want to bring in data to the FPGA over the Ethernet then maybe process it in some way, then send it back.

So far, I’ve looked at nexys a7, arty a7, both of which are about $250 with academic pricing. With international shipping and customs, it might reach $280-$300 which is expensive. There are cheaper boards like Cora but the ethernet pins are connected to the PS and can’t be accessed within the PL.

Are there any other cheaper options?

My objective is building a pipelined CPU, some ports like serial bus and VGA, and just play around with that.

I'm just a student so an Artix 7 will seriously hurt my wallet, but a lot of people speak very good of it.

On the other hand the IceSugar Pro is cheaper, and it works with Apio straight out of the box so I won't have to spend time learning a new ecosystem. But I fear that I will run out of wires eventually.