I am about to finish my PhD. My thesis topic is about analog ic design. I have worked as a hardware design engineer for two years so far. But I would like to get information about the daily and periodic difficulties in the analog design field, which I think makes me feel better. I am eagerly waiting for your advice if you have any.

Happy Saturday! We are a group of students at UC Berkeley looking to understand more about the ins and outs of the chip verification and validation process. Trying to figure out what the biggest pain point for verification and validation engineers is on a regular basis and how much time/energy those pain points consume. Survey is anonymous and should only take two minutes to complete. Would be very appreciative of any insights that this group can offer.

https://berkeley.qualtrics.com/jfe/form/SV_1HYNwwSn6PJPEVM

Greetings all, I did my MS in IC design and working in a setup as analog design and layout engineer for 10months. I'm looking for remote jobs to work as an analog design and layout engineer to earn few more bucks. I have explored linkedin and it ain't helping. Can you please suggest some platforms where I can apply? TIA.

Hi, guys. I am working with open-source EDA tools to design a simple inverter. I'm using Xschem for the schematic and testbench, and NGSPICE for simulation. I'm also using Google’s SkyWater 130 PDK. While I successfully completed the inverter simulation, I'm a bit confused when it comes to layout. I'm using the MAGIC VLSI tool for this. Instead of creating the inverter from scratch, I'm importing the SPICE file generated by NGSPICE during simulation, which helps me get devices like NFET and PFET with their W/L values. After connecting the devices according to the schematic, I perform LVS, and it matches correctly. However, in post-layout, the outputs are not as expected. I think I might be doing something wrong in the layout.

https://preview.redd.it/dbci7ld9shyd1.png?width=406&format=png&auto=webp&s=e67eeb681dd615f123e09358d2911cd131db6fa4

https://preview.redd.it/ybbzeld9shyd1.png?width=1351&format=png&auto=webp&s=e35c9cbc200bbd34b944be2c8e35956b66f3d56a

Hi guys,
Anyone know of how I can find VLSI companies in Dubai. I'm an ASIC Physical Design engineer seeking oppurtunity in Dubai. Could anyone guide me?

Hii I have interview for digital design at cadence design system, plz provide any genuine tips for the preparation of online assessment or interview, which topic to study or so...

I want to pursue a master's program in ECOM, mostly focused on VLSI.

My current CGPA is 7.405, and I'm from a tier 1 college pursuing Electronics engineering and in my 2nd year 1st semester

I have no internships, no projects, no publications, all I had were a few clubs that too I left

Firstly, am I fucked? Secondly, can I make a comeback or at least reduce my fuckery? Please help me, I really wanna pursue and study abroad from a good state university 🙏

I’m starting my search for master’s programs in VLSI and would really appreciate some guidance. My goal is to enter the VLSI industry. I’m open to studying anywhere in the world and would consider either an MS to jump into the industry or a PhD if it enhances my career prospects.

Could you suggest some of the best universities globally for VLSI? For competitive programs, are there specific courses, skills, or tracks I should focus on to strengthen my application? I’m also interested in any solid, slightly less competitive options with strong VLSI training.

Thanks in advance.

Hey everyone!

I’m a Stanford student working on a startup called Instachip (https://getinstachip.com), and I’m looking for beta testers!

We're building the first LLM agents that have internal models of digital logic. Unlike GPT or Claude, our agents don’t just spit out RTL.

Example: when prompted to solve a SystemVerilog problem, our agent actually thinks through it, conducting appropriate timing analysis and creating internal models using Finite State Machines.

https://preview.redd.it/hkvdhuou1dyd1.png?width=790&format=png&auto=webp&s=89393d4efce427357bec179ab7edcb6ad82d706c

We’re working on this with a few folks from OpenAI, MIT and Stanford VLSI Group—and we’re pretty excited about what we’re building, to say the least.

Does anyone want to work with us to beta test?

We’re mainly looking for these three demographics, but we welcome anyone.

1. Engineering managers at chip design/FPGA companies
2. RTL engineers with EDA tooling experience
3. University students interested in chip design

Here’s the sign-up form: https://forms.gle/eJwJToVT5x2JthV88

As for a entry level ASIC design engineer positions in different companies. what are the topics should one be very perfect in for a technical interview and what are the resources to crack the technical interview? How should I start revising?

With 4 years of experience in Cadence SkILL language and Virtuoso Tool, along with proficiency in C++. I am looking to explore new roles. What career paths or industries leverage SkILL language extensively? Also (in Skill) What topics, concepts, or projects should I focus on to demonstrate my expertise ?

I have mostly worked in mixed Signal domain.

Americas flagship chip design and architecture research facility under CHIPs act was announced to be in Sunnyvale California... Anyone excited to make nearly $100k in the heart of silicon valley?

I heard EE is a very desirable job worldwide with the rising chip industry from what I read on this sub EE delves into advanced sciences much more than CE which is more software and coding-focused while looking things up I found out that there are hybrid degrees, I would like to know if you'd recommend that, and any suggestions for good ECE bachelor programs

Hi, I’m a French student specializing in semiconductors. I’d like to know if there is a Discord server dedicated to analog design. If so, could I have the link?

Thanks

Hi everyone! I am curious to see what is a particular circuit or piece of theory in this field that you think is very difficult to deeply understand and comprehend.

Do we have any rtl code sythesis tools which can run on website like edaplayground, i want to see what my code gate level looks like, any tools which run online?

TDC architecture

Hello everyone, I am currently designing a TDC block using SAR architecture. Here I start with designing the SAR logic block. I have read the article but still do not fully understand the behavior of the SAR logic block. Hope everyone can describe in detail the algorithm as well as the block diagram of the SAR logic block. Thank you very much everyone.

https://kobaweb.ei.st.gunma-u.ac.jp/news/pdf/2017/2017ISPACS-rino.pdf

Hi all,

I am facing this issue where I am moving to another team after tapeout of current IC and have been asked to document my current design for future designers. The issue is my company doesn't have a culture of documentation and i dont know how to document it and my manager or coworkers are also clueless. I tried asking around but there is no precedent for it, most of the time, people just guess or take help of text and annotations placed in schematics but that leaves out a lot of crucial info that goes into decision making on choice of devices, sizing etc. I am considering the following aspects and will take a case of simple 5 OTA design:

1. Documentation of all pins to the block as well the expected behaviour of the blocks for all possible combination of control signals. For my 5 OTA, this would mean describing the 3 signal pins, the one pin for biasing, the power rails and the enable signal.

2. Description of the architecture required to achieve the functionality: here i would describe the block in terms of textbook circuit description. For example, for the 5 OTA, i would literally explain the 5 OTA architecture

3. Description of partitioning of sub-blocks: Here i would explain the partitioning of transistors into functional sub-blocks, like which transistors form current mirror, which ones input pair, which ones are just power down switch. I would also explan the sub-blocks specs decided by me, like how much current mismatch i can tolerate in current mirror, how much input error i want for input pair.

4. Description of each transistor and wire - Here i would explain the sizing and nature of each transistor, for example why the required sizes of current mirror, why i chose a certain variety of transistor for the input pair and not the other, which PVT corner were kept in mind while making some unusual choices etc, how many contacts have to be placed on a certain transistor.

So from point 1 to 4, i want to go basically from systems level to the transistor level in my explanations. I came up with this scheme tentatively and wanted to know how to do it systematically without wasting too much time, as i have to document my current design and also finish learning about the systems level documents for my new team during the transition duration of few weeks and i want to spend as much time as possible about learning about my new team.

But i am not sure if the scheme i am proposing will really ensure someone new can understand the design? I dont want to do it in a way where i put significant time in documenting but its so bad that no one can use it.

Looking forward to your inputs, thanks!

Hi all,

I'm currently in the application process to an analog-mixed signal team, full-time position.

The hiring manager said the interviews will mostly include analog blocks like OPAMPs, LDOs, bandgap reference, ADC/DAC but there can also be some DSP and filter questions.

I did some switched-cap filters in the past (FIR and IIR, switched-cap filters for noise shaping in ADCs).

I don't know that field very well so I don't know what kind of circuits are built in that field so I was wondering what kind of questions I can expect regarding those? What can I study? Should it be full-on reading Oppenheimer signal processing book?

Any response is appreciated.

hello can you guys tell if i have any chance at the following universities, I'm applying for fall 2025 intake.

Unis: UT AUSTIN, UMICHIGAN, ETH ZURICH, BERKELEY, GATECH, Texas A&M, ASU, UIUC, CALTECH , UCLA, CORNELL, UW MADISON, NUS, Uni southern California, UMINNESOTA, NC STATE, TU DELFT, TUM, UW SEATTLE (uni of Washington), RWTH Aachen, Penn state.

Ik these are alot of unis but i just put them cause idk which ones i have a chance in, my priority is the first 10 unis.

My profile:
Undergraduate CGPA: 9.3 (passing year: 2024) IELTS: 8..5 (S:8.5, W:7.5, R:8.5, L: 9), will give gre in novermber.

1 IEEE publication on PLL (it was a review paper)

Projects:

• A basic PLL
• Vein Detection using NIR
• RTL to GDS Full adder using cadence tools
• will be doing another project on PLL or something else in VLSI itself

Experience: 1 internship at drdo (an Indian government institution), 1 internship from a private company but this was on pcb design.

Lor:

• one from project guide at the internship
• and the rest 3 or 4 from my university faculty

Could someone pls help me out
Thanks alot

Hi guys,

Can someone help me in understanding gearbox present in serdes.

I cant find much material at my workplace related to that.

if possible please share some materials too...

Thanks

I am curious about the real world use of Universal Power Format (UPF). My understanding is that it used as a specification language for low power devices, so you can check your design at multiple stages to communicate power intent and make sure you adhere to that intent.

From what I gather it sucks to use, and everyone is trying to make auto generators for UPF (e.g. Synopsys Verdi creates UPF from a csv - still not sure how exactly; and SiFive had some work on this that it looks like they dropped: https://github.com/sifive/upf).

When I have talked to engineers who used UPF, they said they used it because their boss told them too. Does anyone else have experience that either matches this or is somehow different?

Hey,

I'm checking the current of my block in a low power state.

From a transient Spectre simulation, it looks fine unless I run it for a very long time (few seconds), in which case it goes too high.

From a DC Spectre simulation it also shows that high current at the port of the block but the devices inside do not show anywhere near that current.

Where is the current disappearing to? Can anyone suggest how to troubleshoot this?

- Iam designing Fully differential 10bit 50MS/s SAR ADC.

- the problem is the comparator input pair is very large to decrease the input refered offset, so it has very large input capacitance which affects the DAC linearity.

- how to solve this problem?

- I see papers/thesis using very small capacitance ~1fF for the capacitive DAC, but I wonder how the linearity isn't affected by the comparator input capacitance.

Is there a way to save the all of the graphs of a simulation in a single JPG file? I tried saving the graphs but it only saved the graphs that was on the screen at the moment of saving (and not the rest of the graphs). Also, is there a way to get the JPG files from the VM to my computer?

I'm a junior IC designer considering pursuing the Purple Certification for AMS circuit design. I'm wondering if it's worth the time and effort, especially for someone early in their career.