Hi Everyone,

I'm working on a fully differential folded cascode opamp, and I've attached the basic design that I'm using below.

Fully Differential Folded Cascode Opamp

I'm a bit confused on how to calculate VB1, VB2, and VB3. I've been trying to find them through trial and error but that doesn't seem to be working. I can't find values that keep all the transistors in the saturation region at the same time. Any advice would be greatly appreciated.

I am currently pursuing ECE 2nd year in Bangalore. SO, I am basically a guy who doesn't like coding and I am interested in vlsi (chip) like ASIC . But Now am not sure where to start in this journey cause i want to pursue a career which requires minimal coding and has a demand in every semiconductor company like synopsys,analog devices,broadcom etc,( I want to learn some proper skills which can be used for various careers in vlsi so that hands on project and extra skills will land a job for a fresher one like me , Any suggestions would be really helpful and appreciated

2024 graduate in electronics and communication Engineering and currently working full time in Telecom sector. I wish to pursue a career in VLSI designing and embedded systems. Any advice is welcome.

I’m new to the job market and I’m applying for jobs in RTL and architecture modeling. I’d like to read other people’s interview experiences and share mine in return. Does anyone know of a relevant place where I can do this?

I'm trying to add FreePDK45 into Cadence Virtuoso, but there isn't a clear guide on how to install it. If anyone has experience on successfully installing and using it, can you please walk me through the process?

Hey guys.. As the title says, does anyone know somewhere that offers a vacancy/training/internship in analog design or layout? Preferably, remotely.. I'm from Cairo, Egypt.. I am ready to relocate if the job requires travelling. Thanks

Would it be possible to design an LNA (just the schematic without the layout) in LTSPICE and perform the simulations required to verify performance or is it necessary to use cadence or ADS?

Hello,

I hope all have seen that the ASML store is currently shipping lego machines. Considering that this is a relative bargain at 230 USD, I'd like to ask about the possible export regulations that may occur when shipping this product? Which authority must I talk to with regards to exporting this technological masterpiece?

https://asmlstore.com/products/twinscan-exe-5000-lego-set

Title.

Does anyone know if there's anything available in Florida?

I'm currently applying to Analog-MS design engineer positions to start after finishing my PhD and all I'm seeing is California, Texas and a handful positions in Boston.

I have been rtl verification engineer for 3+ years, since college days I had dream of authoring my own research papers now since I am in industry and my area is rtl verification, is there any scope of research here? our most of the work concentrates on building environment doing regression analysis and stuff, if this is the only thing we have to do I am bit worried about my career progress,nobody in our team looks like has any idea or will to do something new, anyone can help me with this?

I'm a layman searching for material science reasons why this is not likely. Would appreciate any sources to back up the physics of why low power applications are not a good fit for SiC.

All I can find is the undeniable advantages of SiC technology over Si. Power electronics are obvious. Diodes, IGBTs, and MOSFETs are transitioning to SiC in higher power applications. SiC costs are coming down and lower voltage applications are increasing: Low Voltage Industrial Motor Drives, low wattage QR Flyback Converter Infineon's 15V OptiMOS.

There seems to be memory applications being explored: Memristors, NVSM SONOS or RRAM.

As for low power logic chips, even if costs were equal, replacement is unlikely due to how far ahead silicon technology is compared to silicon carbide.

It seems silicon's one physical advantage is it's higher electron mobility. Can this be addressed through doping and epitaxy?

Energy use is the latest bottleneck to AI data center development. Hyperscalers and developers are demanding more energy efficient solutions. The recent news of Nvidia Blackwells overheating is an obvious inefficiency to be addressed. I understand SiCs role will probably be more supportive than disruptive. Chiplets or SOC will probably need to integrate SiC's more efficient power handling. Or will it mainly be relegated to roles like Infineon's new PSU?

It also appears Photonics is disrupting AI infrastructure. Is this an opportunity for skipping traditional silicon roles with SiC in QPICs, or will this mainly be supportive of getting more out of silicon based architecture?

Thanks for any thoughts on these matters!

Hello all,

I’m currently a computer engineering co-op student at a big semiconductor design company. My role now is to debug graphics issues with the chip in post silicon. I’m wondering how I could transition into design after I graduate.

I have designed a simple processor at school and I’m currently doing a Synopsys UVM + SystemVerilog courses given by the company.

Any tips from the more experienced folk for the younger generation? Thanks in advance :)

I'm a new bachelors graduate (2024) from India. I currently work at Intel as an SoC Physical Design engineer. I work on 18A technology, and I'm learning a lot in this role as it's a purely design role and not verification/validation etc. The pay is decent as well considering the market for a person fresh out of college in India. My interests are always inclined towards CPU RTL /Microarchitecture Design. Granted that I'm currently working in PD, it's still interesting to me in some way.

Now, the tricky part. I received an offer from ARM for the role of Architecture Verification Engineer. I had to go through 6 rounds of interviews. I met the whole team and they made it very clear that this will be a validation/testing role where I write tests in C and Assembly to test ISA level architectures like load/store, branch etc. They also clearly mentioned that I will not be doing any microarchitectural work in any case, so that means no SystemVerilog work, no UVM, no RTL nothing. It's just writing some tests in C and Assembly to verify some ISA level stuff. I had asked them if it was possible to switch to a design based role where I'm actually learning something, but they shot me down by saying it's possible only after 4-5 years of working which doesn't suit me as I also have plans to do a masters/PhD in computer architecture.

The pay for this role is quite high compared to Intel, with a 50-60% increase in base pay, plus they are also giving me RSUs which Intel isn't. So TL:DR, ARM's CTC is almost 2x of that of Intel. And considering the position Intel is in currently, a lot of factors come into play.

I need advice from experienced people here who have worked at ARM or Intel or anyone in this subreddit on what should my next steps be regarding whether I should stick to Intel or move to ARM.
Highly appreciate your thoughts and advice.

I have searched YouTube for RF tutorials and the tutorials I have found so far aren't great. A complete example of block design from specs to schematic, calculations, simulation, layout and parasitic extraction aren't usually presented so I want to see if there are other channels on YouTube or online platforms you guys recommend.

on YouTube, I have found so far that the following are good: Rhode Shwarz, and Anurag Bhargava. So far, I think Anurag Bhargava is really good for ADS.

I want to know what you guys think is the best for learning block design. I realize that theoretical calculations can be very well explained in books (I have read an entire chapter on LNA design) but the translation from hand analysis/concept to software design isn't usually given in textbooks-it's mostly the concept behind the design process. I think it would be great to supplement the understanding on textbooks with a video that explains how to use software to do the actual implementation where everything part of the design process is included.

In spring next year I will be starting my masters thesis. I have not decided on a topic yet. After graduation I want to work in processor/SoC design, e.g. as a Digital Design or Design Verification engineer.

How important is the topic of the Master Thesis when applying as graduate student?

What are some important/interesting topics in your opinion?

What are the advantages/disadvantages of doing the Master Thesis at University instead of with a Company?

One topic candidate that excites me is " Implementation and Evaluation of RISC-V Vector Extension for the Acceleration of 4-bit Precision Neural Networks". Here I would need to do profiling of neural network 4-bit compute kernels and extend an FPGA based open source university vector processor to reduce their cycle count. In the end the instructions should be used automatically in models compiled with Tensor Flow Lite Micro, so I also have to extend the LLVM compiler with support for the instructions.

What do you think of that topic?

Hello everyone, I am currently starting to design an ADPLL. I wonder if anyone has done it or has experience with it? Hope everyone can share. Thanks a lot.

https://preview.redd.it/46w0ljw6z84e1.png?width=733&format=png&auto=webp&s=90404db6f4cf8f0c5df11139075705adb297e7e9

I really need some advice here. Dealing with graduate level circuit design feels like a maze to me. Say I am designing an mixer, oscillator, LNA, or PA. I come across a paper that presents a design that is never seen on textbooks and the analysis only is explained on the paper i am reading and a few others from which the idea was orginated from. The issue is these papers don't always do a good job explaining certain assumptions or simplications or even derivations of the equations used. How do you manage to apply an idea from a previous paper when the information to do so feels incomplete?

I am trying to operate from first principles thinking to build my understanding up but i am struggling.

Have anyone worked there? Is it a good place to work?

Interested in what people in the UK that work in the field did for their education, specifically Master's degree.

//verilog code
module test(input D, C, R, output reg Q);
    always @(posedge C, posedge R)
        if (R)
    Q <= 0;
else
    Q <= D;
endmodule

comment: synthesis script

read_verilog proc_01.v
hierarchy -check -top test
proc
;;

https://preview.redd.it/zza5j64qhs3e1.png?width=910&format=png&auto=webp&s=c44f2b38a6b7d6ea076f435c412018ba35966ad4

source: https://yosyshq.readthedocs.io/projects/yosys/en/stable/using_yosys/synthesis/proc.html

Hey guys, hope you are well. So I wanted to know if there any remote vacancies to apply for as a junior layout designer. Thanks

I am learning about oscillator design and encountered the Nyquist test. I wanted to check my understanding.

A_cL=A_oL/(1-A_oL*B) is the closed loop gain for a positive feedback voltage amplifier. The A_oL*B is the loop gain when the feedback network is broken and not summed into the input. If there are right half plane poles, the oscillator will be unstable. This is required to start the oscillator. As long as the loop gain is more than 1, it will have right half plane poles. Also the nyquist plot will encircle the critical point 1+0j. As long as it encircles 1+0j, it is unstable. However, for the oscillator to stabilize and maintain steady oscillations, the poles must move on to the imaginary axis at which point the loop gain A_oL*B is equal to 1 and the positive feedback amplifier is stable (i think?). The direction of the circle indicates if there are more poles than zeros or more zeroes than poles. poles allude to those of 1-A_oL*B and zeroes allude to those of A_oL*B. The number of times it encircles the critical point is given by N=Z-P where Z are zeroes as mentioned before and P are poles as mentioned before. edit: if you have N=0 then it will be stable. if you have N>0, it will be unstable and if N<0 it will also be unstable as both cases indicate an encirclement of the critical point.

This is the part i am unsure about. I thought stability was reached when the poles lie in the left half plane. the imaginary axis is a borderline case where the critical point, 1+j0, isn't necessarily encircled but the tangent of the circle passes through it.

Hello everyone,

I'm currently diving into the world of analog IC design, and I'm facing some challenges. I have a solid background in digital design — I’ve worked with the OpenLane flow for digital synthesis and completed several RTL-to-GDS projects. However, analog IC design feels like a completely different beast, and I’m struggling to figure out where to start.

In digital design, it’s relatively straightforward: we begin with a black-box approach (inputs/outputs and functionality), write the HDL, verify it, and then move through the ASIC flow to get to GDS. But with analog IC design, I'm unsure about the initial steps, especially when it comes to architecture say you design a 5T OTA or a two stage Opamp design, what are the parameters which will I be drafting in the architecturing stage of the project? . I don’t even know what tools or workflows to use to begin the design process, I'm aware that gm-id methodology exists and I lack practical use of it, while I've done very basic calculations following the gm-id methodology.

As my institute doesn't have access to proprietary tools like Cadence or Synopsys, I’m hoping to learn using open-source tools. I’ve heard of tools like ngspice, Xschem, and Magic but I’m unsure how to piece everything together. Tried doing a CMOS inverter with sky130 pdk in magic and ngspice with basic Trans, DC simulation and DRC.

I’m looking for resources like:

1)Open-source GitHub repositories 2)University courses or open learning platforms 3) YouTube channels 4) Tutorials on how to approach analog IC design from the ground up

If anyone has recommendations or advice on how to structure my learning or where I can find these resources, it would be greatly appreciated!

I'm aware that Analog design is a huge field, I'm planning to do masters In integrated circuits and systems. I wanna have a taste before doing it from an institution as a hobby in a lightweighted fashion like I was doing with the Digital system designs(FPGA and Openlane flows)

NOTE:I have completed Razavi's electronics course and also Ali hajimiris Electronics 1&2 from YouTube, I can say strong that I'm very good at Analog circuit analysis part and have good device physics understanding too.

Thanks in advance for your help!