I'm looking to minimize the frequency variation of an on-chip ring oscillator running at 2MHz, through using either an LDO as its supply voltage, or current-starving it with a current coming from a PTAT current source, coming from a constant-gm core with an op-amp within to reduce channel-length modulation inaccuracy.

I simulated the ring oscillator with both structures having the same power consumption to make the comparison more fair. I generated the VREF for the LDO as a simple 2T voltage reference (the one with native and high-threshold NMOS), because I'm on a power budget. Keep in mind, this circuit itself has some PVT and supply variation.

To my surprise, the PTAT current starving actually gave me better PVT insensitivity compared to LDO and I cannot really justify it with theory.

The only explanation I could come up with is that the resistance in the PTAT core tracks the PVT in the same way as the NMOS/PMOS in the ring oscillator.

I would appreciate it if you could please help me understand this better. I'd like to repeat, PTAT core and the LDO runs at the same power, so LDO bandwidth is not too great so it might be related to its settling too.

Best.

I recently fell in love with the field of analog VLSI and realized I should’ve went with an EE degree instead of a CompE degree. As a junior about to enter senior year, I’m debating on either switching to EE (would take 3 extra quarters maximum so 1 academic year ) or just trying to get accepted into a masters program for EE. I talked to a professor and he said I’m only missing two or three classes relevant to analog (Electronic and analog circuits 2, electromagnetism, possibly power systems) and as long as I take the VLSI and DSP courses as electives I have a good chance of getting into that industry.

Every online source I look at seems to suggest a bachelors in EE is a requirement on top of a masters but I’m wondering if a bachelors in CE and masters in EE would be fine? I know sometimes they want a PhD and I’m willing to go down that road in the future, I just want advice about if my degree is relevant enough or if it’ll count against me and I should just switch to EE

(This is posted in 3 other communities CompE, EE, and ECE)

I am from India. I completed my master's today, still being unable to get a job. My thesis was on ADC design, and previously I had designed analog blocks like reference circuit, OTA and other amplifiers. Also, have some experience of the full custom ASIC design flow. So, my whole background is filled with analog. For the past 9 months, I applied to every big and small company that my linkdin profile showed. Only got one interview, was told to work without pay. Big companies atleast send rejection notification, smaller one's doesn't even bother. What's to do? I have some savings, it's not much. I used to get scholarship, which is now stopped. Companies always prefer experience, which is harder to get. Internships are rejecting also, mostly unpaid. Should I leave this field?

Im a bit confused about different jitter types and terminologies. In cadence the two types of jitter that I am able to simulate is Jc and Jcc, these are not what I need. Pnoise simulation has different type of jitters but none of them is edge to edge jitter. Can anyone who has experience with simulating edge-to-edge jitter help me out?

Hi all, I have been working in semiconductor industry for almost 6 yrs now. In those years, I have never been happy to what i'm doing. Yes I should have quit but there's always something bugging me not to do it. I always have this optimistic view that someday I will succeed in what I do and earn more money to it. It is so discouraging to think that IC design is a very demanding job but doesn't really pay you enough (low salary). I remember a colleague of mine saying "We IC designers / Electronics Engineers compared to a Tech Sales Man, we earn less and they earn more. We squeeze our brains to solve complex problems only to have a mediocre salary". I might be mediocre , but I was able to complete multiple projects and with the experience that I have i think i deserve more (salary) but they're not giving it to me. Also there's no career growth, I have been doing the same thing over and over again.

What about you guys? Do you feel the same? Can you imagine yourself working in semiconductor companies in the next 15 years? I know it is a promising job because of the demand, but is it really worth it ?

I need your thoughts before I send my resignation letter, I might change my mind :))))

Hi everyone,

I'm reaching out to seek some career advice, particularly from those in the electronics engineering field. Currently, I'm working in the semiconductor industry, specializing in analog design. However, I find myself constantly overwhelmed and stressed in my role.

Here's a brief overview of my situation:

I relocated from a different country, which has presented numerous challenges in adapting to my current role. Last year, I experienced almost a burnout while completing my master's thesis, resulting in a less-than-excellent grade that significantly impacted my confidence.

At work, I struggle with even the simplest tasks and find myself constantly asking questions. While the company encourages seeking clarification, I can't shake the feeling of incompetence each time I seek assistance. Moreover, I often feel humiliated when my work is criticized or deemed incorrect, adding to my already high levels of stress and anxiety.

Beyond work-related challenges, I'm also grappling with personal struggles. I'm dissatisfied with my current living situation—the salary isn't as high as I'd hoped, and I live in a country with unfavorable weather and food. Feeling isolated and without any friends further contributes to my overall unease.

Additionally, I'm exhausted from constantly feeling behind in life at everything, which only heightens my stress and anxiety levels. While I understand that happiness shouldn't solely depend on one's job, finding fulfillment in my work is crucial to me.

Ideally, I'm seeking a role that offers a good salary, remote work flexibility (which is my preferred working method), and tasks that I can handle independently with a reasonable learning curve.

Some potential paths forward that I've considered include exploring opportunities in writing or educational roles, transitioning to a position with lighter design responsibilities that better align with my strengths, pursuing another master's degree from a reputable university to bolster my skills, or exploring career paths more focused on education, where I can make a meaningful impact.

However, I'm feeling overwhelmed and uncertain about which direction to take. Any advice or insights from those who have navigated similar challenges would be greatly appreciated. Thank you in advance for your help and guidance.

Hello, I'm a junior physical design engineer and I want to get a training on FinFET physical design. Do you recommend any training course to get?

Hello all,

So I have been working with a specific PDK for Cadence designing and simulating analog circuits with Virtuoso and ADE. When doing the physical layout however, the files provided for the verification rules are intended to be used with the Siemens Calibre software (which I don't have access to), they have a .cal extension and the syntax is different than the .rul files that I have seen for other PDK's.

Does anyone know of a way to automatically transform this kind of files? Should it be done manually? Should I just start crying?

I'm planning on doing a project based on human senses, taste and touch in particular. I need guidance where and how to start with it. I have basic understanding of electronic components and its uses, so hopefully designing a circuit will be easier. But is there any roadmap of creating a new circuit design..

Greetings everyone,

I am a master's student venturing into an internship focused on low-power RTL, I'm seeking guidance to enhance my understanding before diving in (I do not have a job ex, and have done fairly simple RTL projects which basically just focused on getting the correct outputs ). The company has kindly suggested a refresher on several crucial topics. Could you recommend some quality resources?

1. Power/Energy Calculations in CPUs/GPUs: I'm particularly interested in delving deeper into concepts such as Perf-per-Clock versus Perf-per-Watt, exploring the factors influencing power and energy consumption.

2. Low Power Architecture/Logic Design Techniques: Any insights into innovative approaches and methodologies for designing low-power architectures would be greatly appreciated. Any youtube playlists or books I could refer to would be of a huge help!

3. RTL/Logic Design Optimization for Power and Timing: I'm eager to learn about the various optimizations and techniques available for lowering power consumption and improving timing performance at the RTL/logic design level.

Your suggestions and recommendations on reputable resources for these topics would be immensely helpful. Thank you in advance for your assistance!

I'm currently working on finding the transimpedance gain of a transimpedance amplifier. However, I've encountered an issue where I'm getting different gains when performing AC analysis compared to S-parameter analysis.

For the S-parameter analysis, I'm using a formula from a specific research paper (Link) to find the gain from S-parameters. The Formula says ZT=Zo*S21/(1-S11).

After calculating the gain from the S-parameters, I noticed that the gain is different from what AC analysis gives. I'm unsure if the Formula I'm using is correct or if I'm missing something in my calculations.

I do not terminate the 50-ohm impedance port at the input in the AC analysis.
However, for the S-parameter analysis, I do apply the 50-ohm termination.

Could anyone provide some insight into this? Is there a reason why these two methods would yield different results? Any help would be greatly appreciated. Thank you!

Circut Diagram for sparameter and ac analysis

Results

Posted this on ECE some days ago but forgot to post it here too :)

Hello, I'm a not-US based person working at a company that designs high-performance CPUs (most of my coworkers are in US). I work at a Pre-Si CPU performance verification team, helping RTL designers and architects debug microarchitecture performance features making sure they're what architects expect. Project, team and job is exciting, there are a million things to learn and develop.

The issue is the company itself, it feels like a sinking ship. On the last years the same narrative is told: "Hang on, just a few more years and we will succeed". Next year we get the same story.

When comparing my job/compensation to other persons that work in similar fields I see that I deal with both more things and more complexity than them with similar or less pay. We're understaffed too, management keeps pushing aggressive deadlines. We deliver things because we're working 9-10 hours per day + weekends too (with no overtime of course)

I've never tried interviewing for another company but I feel like the grass looks much greener on the other side.

I keep hearing that this area and job is always super hard, coworkers/managers/senior engineers compliment my work constantly but I still earn the same as other friends in smaller companies with jobs that are not as specific/complex as mine.

Would you recommend to wait and get as much experience as possible here before thinking about moving to a different company? What would you do? Thanks.

I am design a gain boosted folded cascode amplifier using common mode feedback circuit as part of project in cadence virtuoso in gpdk 180nm tech, I designed the opamp with around 32dB gain , Vdd used is 1 V, the research paper I am referring to has sizes of the transistors, can anyone guide on how to bias the transistors so that all go into saturation?

Is it just me or do others also find that some books 'click' with you more than others for explaining concepts.

For example, I sometimes find Razavi's explanations very thorough but mathematically heavy and by the end of a subsection, I no longer intuitively understand the circuit.

A great example is in the explanation of low voltage cascodes, it gets confusing quite quickly as I believe he is doing his best to be thorough. Other books condense the topic to its core and explain that first, with rigor either left out or added later.

Is it normal to switch books for certain concepts? Or should I be understanding everything in Razavi.

I want to design vco with these specifications

• 1.2 supply or lower

• 10 Ghz mainly

-good phase noise , tolerance to substrate and supply noise

-torlerant to variations

There so many techniques out there that i am overwhelmed

Should i use passive resitor based differential delay cells to ensure small variations and better noise performance?

Or some sort of controlling loop to counter variations in case i used supply current ?

Should i use some sort of freqency doubler to enhance phase noise?

Is it a must to use some sort of duty cycle correction after the outpur of vco?

The size of M1-M4 has an effect on gain, phase margin, bandwidth, etc. However, does the size of M5 have anything to do with these? The only thing I can think of is that the W/L of the M5 limits the input common mode range. So does this mean we can minimise the length of the M5 to save area?

Schematic of a 5T OTA

"the CPU is really just an electronic interpreter for machine code. we can then target this machine code when compiling"

I saw this in a comment in a post asking about compilation and interpretation in programming languages. As a beginner who is interested in the hardware and software, I wonder if this perspective is true.

Hello all, I'm starting to study about noise and it's impact on analog/rf circuits. So apart from razhavi sir's book is there any other online resource available? Video, pdf, ppt anything you'd like to suggest? N.B: apart from basic theory, I'm more interested in finding the noise of a given circuit or how intuitively we can reduce noise of a given circuit... Any kind of resource on this would be world to me.

Hi, I am trying to design a linear regulator. I started with macromodel for the error amplifier and added a pass stage. 50mA idc is the load. My desired output is 1.5V and Vin=1.8V. IBM180nm models. Vref or vinput to reg is 500mV and beta is 1/3.

There is something strange happening. As shown in the attached picture, my output is 1.503V. however high my loop gain would be, my output cannot be more than 3*500mV i.e. it cannot exceed 1.5V. it has to be always less than 1.5V so that vout= (A/1+A(beta)).Vref is obeyed. Can anyone suggest what might be ths issue.

When i model the pass gate with a vcvs, i get the expected output.

When they say snapdragon 8 gen 3 is built using a 4nm process, does it mean the channel length of the transistor is 4nm?? Because I've seen that Intel 7nm doesn't really means 7nm but it's just a marketing term. So have we really achieved 4nm??

Also Intel has recently acquired the high NA EUV lithography machine. What transistor size will it be capable of fabricating??

Any recommendations?

I'm currently in search of someone who can lend their expertise in troubleshooting a multistage amplifier design. If you have experience in this area and are willing to assist, please let me know. I'll send you a private message to discuss further details.

Looking forward to connecting with you.

Thanks!

Hi Gang, (and apologies if I am not addressing the best community).

I am looking for component part recommendations for the discrete transistors same as (or similar to) those used Monster 6502 project (Eric Schlaepfer please feel free to chime in). Specifically the 2 versions of N-FET transistor(s), The single transistor device and the Quad transistor (with common substrate connection or a similar Dual transistor). I am looking at doing projects/designs which are not as extensive/ambitious as the Monster 6502 but in about the same voltage/current domains (Logic level).

I have looked at several of the Youtube videos about the Monster ( Wow what a cool project! ) and some of the available documentation (but I have not found these transistors explicitly identified). So I am using this to get recommendations for parts for my design. I consider myself a sophisticated circuit designer however my knowledge of commonly used discrete components is very limited. So I could see myself selecting some obscure (not commonly used) component with no justification other than my ignorance. And while I am looking at the components used in the Monster 6502 project, I will gladly take recommendations for devices that are probably similar. For example the BSS138 as a single transistor device in the SOT-23 surface mount package. In addition I would also consider recommendations for a single transistor device with a separate substrate connection. (In the BSS138 the Substrate is tied to the Drain, and on the Monster 6502 project page they say such a device was hard to find as a single, so they went to a Quad-Transistor package when needed to implement transfer .

My Background: I am retired but in a previous life (In the 1980's) I was a Full Custom chip designer (working in N-MOS and later CMOS) designs of microProcessors and related peripheral chips. I transitioned to embedded (mostly SW) application after that. (Edit: (working in depletion-load NMOS logic similar to that used in the original MOS6502 design on a 4um node and later in CMOS logic on a 2um node ... just to be a little more specific)).

I did post layout simulation for a CMOS inverter. I used "Cadence Virtuoso" software for the simulation. First I created a configuration file. I did the transient analysis for input voltage versus output voltage to compared the performance of schematic design and the layout design. I used the parasitic capacitors and resistors from the RC extracted view for simulating performance of my layout. I measured the fall time delay between the two waveforms. There was small but noticeable difference between the two. Here is the link of the video https://youtu.be/afRU5P2FbRU

Hello, I am working for a semiconductor company as an analog design engineer. But most of my work is in design verification and methodology bringup.

I have a masters degree with focus on analog design, but have never done any real design outside academic projects.

I would like to start investing some time in improving my analog design skills with practical design projects. I have access to cadence and commercial pdk. I try to read academic books, but I think it’s better to start practical design and then refer the books for better understanding.

Topics of interest

• ADC
• SERDES
• VCO/PLL

Can anyone recommend sample projects and spec targets? Also, I would really appreciate it if you can give any guidance related to this.

Just yesterday I received an invitation to a 2hr in-person interview for a Design Engineer position at ARM.

By this point, I had only previously had a brief 5-minute chat with one of their recruiters. I also wasn’t initially told who would be interviewing me, or the nature of the interview.

Is this normal?

I feel like usually there is an intermediate step before jumping into such an invested interview (e.g a 30min screening call with the hiring manager or similar).

EDIT:

A lot of solid advice in the comments!

I’d like to clarify that my original post was more directed to asking if it’s normal to go from a 5min call with recruiter to a 2hr technical interview. My experience so far has been that there is usually some intermediate stage in between the two.

This role is in the UK, and doesn’t have specific YoE requirement but is not grad level (I would assume 2-5yrs in this case).