Hey everyone,

I'm currently working on a project where I need to split the workload between a Nios V processor and an FPGA. Specifically, I have a codebase where the heavy calculations will be offloaded to the FPGA, while the Nios V handles other tasks. However, I'm relatively new to this aspect of FPGA programming and could use some guidance on how to establish communication between the Nios V and FPGA.

Could anyone here share their experiences or insights on:

1. Recommended communication protocols or interfaces for linking Nios V and FPGA?
2. Any pitfalls or common challenges I should watch out for?

Additionally, if anyone has examples or resources they could point me towards, that would be incredibly helpful.

Thanks in advance for any assistance or advice you can offer!

Hello r/FPGA, I been feeling very conflicted recently about the way I spend my time and my future career.

See, I am a 4th undergrad computer science student who spend vast majority of my time studying deep learning. But starting about a year ago I found that I have became addicted to FPGAs.

Originally it was just an urge to learn about FPGAs because I was obsessed with getting more compute power for my deep learning projects.

However, the more time I spend working with the FPGA the more I realize that if I want to get the most amount of compute power I would have to dig deeper. I find myself planning out all of my time to learn more about FPGAs rather than deep learning.

This has made me feel very conflicted because it looks like there is very little career opportunity for a person with a mix of deep learning and FPGA skills. Kind of like “jack of all trades but master of none” type of situation.

So I was just wondering what should I do, would it be more responsible to drop FPGAs and focus on deep learning or should I keep at it with FPGA and hope industry is ok with a CS major rather than a EE major.

Hello Chaps

I have a problem with the divide operetor, i have the following variables:

int the_period = 600;

real the_time_difference = 2;

when I am doing the next operation the_period/the_time_difference i got 30 , and I can't figure it out why, can someone help me?

I’m trying to pursue a career in this field. How can I be competitive? Is it super hard? Can anyone refer me?? 😂

I'm not sure how a masters works but I wanted a technical masters that allows me to do different subfields that relate to FPGAs. Just now sure what they are aside signals.....

People have mentioned before on taking a masters in ECE but not the type of classes to take outside of everything related to DSP....

Hi.

I'm trying to dump some data into a ROM using XPM_SPROM macro (https://docs.amd.com/r/en-US/ug1485-versal-architecture-premium-series-libraries/XPM\_MEMORY\_SPROM)

Values I used are :

xpm_memory_sprom #(
.ADDR_WIDTH_A(10),              // DECIMAL
.AUTO_SLEEP_TIME(0),           // DECIMAL
.CASCADE_HEIGHT(0),            // DECIMAL
.ECC_MODE("no_ecc"),           // String
.MEMORY_INIT_FILE("rom_initialization_file.mem"),     // String
.MEMORY_INIT_PARAM(""),       // String
.MEMORY_OPTIMIZATION("true"),  // String
.MEMORY_PRIMITIVE("block"),     // String
.MEMORY_SIZE(32768),            // DECIMAL
.MESSAGE_CONTROL(0),           // DECIMAL
.READ_DATA_WIDTH_A(32),        // DECIMAL
.READ_LATENCY_A(1),            // DECIMAL
.READ_RESET_VALUE_A("0"),      // String
.RST_MODE_A("SYNC"),           // String
.SIM_ASSERT_CHK(0),            // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
.USE_MEM_INIT(1),              // DECIMAL
.USE_MEM_INIT_MMI(1),          // DECIMAL
.WAKEUP_TIME("disable_sleep")  // String
)

I'm trying to understand how will this be organized in BRAM ? Will it be 1024 rows of 32 bits each ? And if I give 0x0 and 0x01 as read address will it read out first and second 32 bits ?

Packt has published "FPGA Programming Handbook: Transforming Modern Systems with SystemVerilog"

As part of our marketing activities, we are offering free digital copies of the book in return for unbiased feedback in the form of a reader review.

Here is what you will learn from the book:

* Master FPGA programming with SystemVerilog and program FPGAs using the latest design methodologies

* Understand hardware description languages like Verilog and VHDL used in FPGA design flows

* Explore advanced topics like system-level verification, high-level synthesis, and co-simulation

* Learn best practices for optimizing logic, routing, and achieving timing closure in FPGAs

If you feel you might be interested in this opportunity, please comment below on or before 29th April 2024.

Altera annouced with Quartus 24.1 , Agilex5 is now ready to program.

See link, go to DOWNLOADs --> TAB "Individual Files" --> Scroll down to "Agilex5" ;-) ;-) ;-)

https://www.intel.com/content/www/us/en/software-kit/819138/intel-quartus-prime-pro-edition-design-software-version-24-1-b115-for-windows.html

​

In the Intel Donwload Center are 233 docs to AGILEX5.....WOOOWWW, a lot to read. ;-) (Maybe you need to login before.)

Agilex™ 5 FPGA and SoC FPGA Product Overview (intel.com)

​

Also Arrow Electronics, who has the first worldwide available Devkit for Agilex5, has launched their Github....

https://github.com/ArrowElectronics/Agilex-5/wiki/Agilex-5-E-Series-AXE5-Eagle-Development-Platform#reference-designs

​

Now let's see how this 10nm FPGA performs vs. all other 16nm TSMC FPGAs in the midrange. ;-)

​

​

​

​

​

I'm writing the source code for Vending Machine FSM:

module vending_machine(
    input   clk,
    input   nickle, dime, quarter,
    output  reg soda,
    output  reg [3:0] change
    );
    //parameter for state assignment
    parameter   S0  =  4'd0,            //soda = 0, change = 0
                S5  =  4'd1,            //soda = 0, change = 0
                S10 =  4'd2,            //soda = 0, change = 0
                S15 =  4'd3,            //soda = 0, change = 0                
                S20 =  4'd4,            //soda = 1, change = 0
                S25 =  4'd5,            //soda = 1, change = 5
                S30 =  4'd6,            //soda = 1, change = 10                
                S35 =  4'd7,            //soda = 1, change = 15               
                S40 =  4'd8;            //soda = 1, change = 20
    //parameter for the change
    parameter   C0  =  3'b000,          //change = 0
                C5  =  3'b001,          //change = 5
                C10 =  3'b010,          //change = 10
                C15 =  3'b011,          //change = 15
                C20 =  3'b100;          //change = 20        
                                     
    reg [3:0] state, next_state;
    
    //input equation (ref: state diagram)
    always @(*) begin
          case (state)
          S0: case({nickle, dime, quarter})
          3'b100: next_state = S5;
          3'b010: next_state = S10;
          3'b001: next_state = S25;
          default: next_state = S0;
          endcase
          S5: case({nickle, dime, quarter})
          3'b100: next_state = S10;
          3'b010: next_state = S15;
          3'b001: next_state = S30;
          default: next_state = S5;          
          endcase
          S10: case({nickle, dime, quarter})
          3'b100: next_state = S15;
          3'b010: next_state = S20;
          3'b001: next_state = S35;
          default: next_state = S10;
          endcase     
          S15: case({nickle, dime, quarter})
          3'b100: next_state = S20;
          3'b010: next_state = S25;
          3'b001: next_state = S40;
          default: next_state = S15;
          endcase      
          S20: case({nickle, dime, quarter})
          3'b100: next_state = S5;
          3'b010: next_state = S10;
          3'b001: next_state = S25;
          default: next_state = S20;
          endcase      
          S25: case({nickle, dime, quarter})
          3'b100: next_state = S5;
          3'b010: next_state = S10;
          3'b001: next_state = S25;
          default: next_state = S25;          
          endcase  
          S30: case({nickle, dime, quarter})
          3'b100: next_state = S5;
          3'b010: next_state = S10;
          3'b001: next_state = S25;
          default: next_state = S30; 
          endcase      
          S35: case({nickle, dime, quarter})
          3'b100: next_state = S5;
          3'b010: next_state = S10;
          3'b001: next_state = S25;
          default: next_state = S35;          
          endcase   
          S40: case({nickle, dime, quarter})
          3'b100: next_state = S5;
          3'b010: next_state = S10;
          3'b001: next_state = S25;
          default: next_state = S40;
          endcase 
          default: next_state = state;
          endcase                          
    end

    //Seq logic
    always @(posedge clk) begin
        state <= next_state;
    end

    //output equation
    always @(*) begin
          case(state)
          S0:  begin soda = 0; change = C0; end
          S5:  begin soda = 0; change = C0; end
          S10: begin soda = 0; change = C0; end
          S15: begin soda = 0; change = C0; end               
          S20: begin soda = 1; change = C0; end
          S25: begin soda = 1; change = C5; end
          S30: begin soda = 1; change = C10; end
          S35: begin soda = 1; change = 15; end     
          S40: begin soda = 1; change = 20; end  
          default: begin soda = 0; change = C0; end            
          endcase
    end
endmodule

I know you not read my code but just take a quick look at //input equation, It's clear that I use "{nickle, dime, quarter}" so the input of DFF should include the nickle, dime, quarter wire.
However, based on the RTL Schematic:

https://preview.redd.it/5az6y3a1ihvc1.png?width=1151&format=png&auto=webp&s=8069d5b3b75054ba858d55c9970b7a7a72a94ff7

Wow, the RTL_MUX with select port is next_state. Its seem like, the input D of DFF does not need some coins to compute the value for it. Just the next_state.
Is there any problem ?

I have a design in vivado that we used export_sim on to the compilation script for the xilinx ips. I'm having confusion on one aspect and problems with another.

The confustion comes that we are using the -use_ip_compiled_libs flag and yet the generated compile.do script still is compiling several xilinx that are precompiled when the com_simlibs command is run. This isn't hugely problematic, but it does generate warnings when questa overwrites the existing libraries. Why is the generated xilinx script recompiling these xilinx libraries instead of referencing the precompiled libraries?

The problem is in the axi_lite_ipif_v3_0_4 library. When running the script questa says that the axi_lite_ipif_v3_0_4.ipif_pkg has changed. I don't see how it could have changed as A) it's not my code B) I'm compiling it in that script. This happens even if I delete the pre-compiled libraries and have it used exlusively what is used in the script.

THe exact error message is:

** Error: (vcom-13) Recompile axi_gpio_v2_0_28.axi_gpio because axi_lite_ipif_v3_0_4.ipif_pkg has changed.

Any advice would be appreciated.

I’m trying to use ethernet for a project I’m working on. Unfortunately the DE10-Lite does not have an ethernet port. However, Quartus has the “Triple-Speed Ethernet Intel FPGA IP” available. Does anyone know of any attachments I can buy for my board to make use of this IP?

Hi,

I've had a fair bit of digital design/verification expereience in the past and I want to venture into cache/memory system design. I was wondering if ppl could point me to techniques commonly found on last level cache design? Or could someone perhaps illustrate how a high performance LLC would look like in industry?

tl,dr: I'm an ASIC design engineer evaluating formal methods as a way to improve my design process by finding more bugs in the design phase. During this process, I found formal tools very ambiguous and inconclusive. I would like to know the opinion of others who have experience with this.

Now a detailed story:

I tried learning to use formal methods to verify my RTL. u/ZipCPU 's blog is probably the best resource on the internet right now. I did many of the exercises in his verilog slides and then sat down to write myself a series of steps I should follow every time I tried to verify a design of mine. For this, I choose two articles article1 and article2. In the first article, a very simple block of code is tested. It looks like:

module	kitest(i_clk, i_reset, i_ce, i_in, o_bit);
	parameter		LN=16;
	//
	input	wire		i_clk, i_reset, i_ce, i_in;
	output	wire		o_bit;

	reg	[(LN-1):0]	sa, sb;

	initial	sa = 0;
	initial	sb = 0;
	always @(posedge i_clk)
	if (i_reset)
	begin
		sa <= 0;
		sb <= 0;
	end else if (i_ce)
	begin
		sa <= { sa[(LN-2):0], i_in };
		sb <= { sb[(LN-2):0], i_in };
	end

	assign	o_bit = sa[LN-1] ^ sb[LN-1];

We want to prove that both 'sa' and 'sb' always have equal contents, meaning o_bit is never asserted. so we add the assertion:

always@(*) assert(!o_bit)

Running yosys with 'smtbmc' engine failed induction on this. The trace shows that 'sa' and 'sb' start of at different values, and eventually i_ce is asserted enough times that o_bit gets asserted and proof fails.

At this point, I chose to try things out from my own understanding. So I did the following:

1. I added an assumption stating i_reset is asserted on each run.
2. I added an assertion stating that if i_ce is not asserted, both sa and sb remain stable.
3. I added an assumption that in the clock post reset both sa and sb become 0.

Even with all this in place, induction failed by starting sa and sb with different values. Realizing I have spent about 20 mins on a block with barely 10 lines of logic and no bug to begin with, I looked at the article for the solution. He faced the same kind of behaviour, but didn't add any reset and initial value related assertions. Instead, changing the prover engine to 'abc' or 'ypr' immediately worked. He also achieved a proof with smtbmc by playing around with the depth parameter and i_ce assertions but it's unclear to me how that step was logically arrived at.

Whereas in the second article where an AXI Lite slave was being tested, lots of assertions were written related to the initial state and resets. It's not coherent what the process is, of coming up with the right set of properties for each unique design.

Now the questions:

1. My designs at work are at least 50 times larger than the one above. How am I to understand if there is actually a bug or the tool is taking me for a ride? Things are definitely not as obvious there.
2. For a verification person with lots of experience, these insights into the tool might be obvious and easy to fix, but for a designer does it even make sense to spend so much time setting up the properties?
3. People who use formal or have seen it being used at work, in what kind of settings does it make sense? Do all tools have quirks like this? (we have the synopsis vc formal tool at work).
4. How many companies actually value the skill of formal verification in a designer?

If i am understanding it right, FPGA's and quartus allows us to build our logic for the controllers, HLSM's, and to verify that they work properly. But to build the controller hardware, what do they use in the industry?

Hi everyone! Forgive me if this has already been covered, but I've been browsing a lot of topics about finding the right FPGA board for a beginner, and to be honest, I'm a bit lost at the moment. I had the opportunity to work with Xilinx Zynq 7000 boards during my final year of study, but as you can imagine, I can't afford to buy one for myself. So I'm looking for an FPGA board that costs less than 200 €/$. My aim is to carry out small sensor analysis projects and, if possible, to display a video output. I'm a bit at a loss as to how to go about it, because in class I've only done basic exercises with flip-flops and simple projects.I've been asking around and I'm hesitating between the "Digilent Arty S7", the "Basys 3 artix 7", however I'm not closed to trying Altera but I don't really have any idea of the possible differences (I've searched but I haven't found anything understandable at my level).So if you have the time and if you could advise me that would be nice.

So, I see 3 use cases:

1. ‘enable’ as reset
2. ‘enable’ as signal for transition from IDLE state
3. ‘enable’ as clk_en

What is correct path?

Hello!

I have been working on a breakout game for a class project, and I am having some issues programming my board with the design. (I get no display output.) I am certain that something is wrong with my code, but I am not too sure where exactly. Hopefully, someone more knowledgeable could provide some insight. I have included my code below.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity breakout is
    Port ( CLK : in STD_LOGIC;
           RESET : in STD_LOGIC;
           HSYNC : out STD_LOGIC;
           VSYNC : out STD_LOGIC;
           BLANK : out STD_LOGIC;
           SYNC : out STD_LOGIC;
           CLKVGA : out STD_LOGIC;
           R, G, B : out STD_LOGIC_VECTOR (7 downto 0);
           LEFT_BTN, RIGHT_BTN : in STD_LOGIC);
end breakout;

architecture behavioral of breakout is
    signal clk25MHz : std_logic := '0';
    signal clk5Hz : std_logic := '0';
    signal clkCounter : integer := 0;
    signal hCounter : integer range 0 to 799 := 0;
    signal vCounter : integer range 0 to 524 := 0;

    -- Sync pulse and display time constants
    constant hSyncPulse : integer := 96;
    constant vSyncPulse : integer := 2;
    constant hDisplay : integer := 640;
    constant vDisplay : integer := 480;
	 
	 -- paddle dimensions
	 constant paddle_width : integer := 60;
	 constant paddle_height : integer := 10;
	 signal paddle_x : integer range 0 to hDisplay - paddle_width := (hDisplay - paddle_width) / 2; -- centers paddle initially
	 
	 -- brick dimensions
	 constant brick_width : integer := 40;
	 constant brick_height : integer := 20;
    constant bricks_per_row : integer := hDisplay / brick_width; -- calculate number of bricks per row based on display width
    constant brick_rows : integer := 5; -- number of rows of bricks
    type brick_array is array (0 to brick_rows-1, 0 to bricks_per_row-1) of std_logic;
    signal bricks : brick_array := (others => (others => '1')); -- initialize all bricks as present ('1')
	 
	 -- Ball dimensions and position
    constant ball_size : integer := 10;  -- Size of the ball
    signal ball_x : integer range 0 to hDisplay := hDisplay / 2; -- Start in the middle of the screen horizontally
    signal ball_y : integer range 0 to vDisplay := vDisplay / 2; -- Start in the middle of the screen vertically

    -- Ball movement speed and direction
    signal ball_dx : integer range -5 to 5 := -2; -- Horizontal speed and direction
    signal ball_dy : integer range -5 to 5 := -2; -- Vertical speed and direction

begin
    SYNC <= '1';

    -- Clock division to generate 25MHz and 5Hz clocks
    clkDiv: process(CLK)
    begin
        if rising_edge(CLK) then
            clk25MHz <= not clk25MHz;
            CLKVGA <= clk25MHz;
            if clkCounter = 5000000 then
                clk5Hz <= not clk5Hz;
                clkCounter <= 0;  
            else
                clkCounter <= clkCounter + 1;
            end if;
        end if;
    end process;

    -- Horizontal and Vertical counters for VGA timing
    hCounterProcess: process(clk25MHz, RESET)
    begin
        if RESET = '1' then
            hCounter <= 0;
        elsif rising_edge(clk25MHz) then
            if hCounter = 799 then
                hCounter <= 0;
            else
                hCounter <= hCounter + 1;
            end if;
        end if;
    end process;

    vCounterProcess: process(clk25MHz, RESET)
    begin
        if RESET = '1' then
            vCounter <= 0;
        elsif rising_edge(clk25MHz) then
            if hCounter = 799 then
                if vCounter = 524 then
                    vCounter <= 0;
                else
                    vCounter <= vCounter + 1;
                end if;
            end if;
        end if;
    end process;

    -- Generating HSYNC and VSYNC signals
    HSYNC <= '0' when (hCounter < hSyncPulse) else '1';
    VSYNC <= '0' when (vCounter < vSyncPulse) else '1';
	 
	 --Paddle logic
	 paddle_controller: process(CLK)
	 begin
		if rising_edge(CLK) then
			if LEFT_BTN = '1' and paddle_x > 0 then
				paddle_x <= paddle_x - 2; -- moves paddle to the left
			elsif RIGHT_BTN = '1' and paddle_x < hDisplay - paddle_width then
				paddle_x <= paddle_x + 2; -- moves paddle to the right
			end if;
		end if;
	 end process;
	 
	 -- Unified Process for Ball Dynamics
    ball_dynamics: process(clk25MHz)
    begin
      if rising_edge(clk25MHz) then
      -- Initial condition for resetting the ball when missed by the paddle
      if ball_y >= vDisplay then
         ball_dy <= -2;  -- Start moving the ball upwards
         ball_y <= vDisplay / 2;  -- Reset the vertical position to mid-screen
      -- Collision with bricks
      elsif ball_x >= 0 and ball_x < hDisplay and
            ball_y >= 0 and ball_y < brick_rows * brick_height and
            bricks(ball_y / brick_height, ball_x / brick_width) = '1' then
            ball_dy <= -ball_dy;  -- Reverse the vertical direction
            bricks(ball_y / brick_height, ball_x / brick_width) <= '0';  -- Remove the brick
      -- Paddle collision detection
      elsif ball_y + ball_size >= vDisplay - paddle_height and
            ball_y < vDisplay and
            ball_x + ball_size > paddle_x and
            ball_x < paddle_x + paddle_width then
            ball_dy <= -ball_dy;  -- Reverse the vertical direction on paddle hit
      -- Top or bottom boundary collision
      elsif ball_y <= 0 or ball_y >= vDisplay - ball_size then
            ball_dy <= -ball_dy;  -- Reverse direction at top or bottom boundaries
      end if;

      -- Regular vertical position update, if no collisions cause a reset
      if ball_y < vDisplay then
         ball_y <= ball_y + ball_dy;  -- Update the ball's vertical position
      end if;
      end if;
    end process;

	 
  -- Display control process
display_controller: process(clk25MHz, hCounter, vCounter)
begin
    if rising_edge(clk25MHz) then
        -- Control BLANK signal based on active display area
        if hCounter < hDisplay and vCounter < vDisplay then
            BLANK <= '0';  -- Active video period
            -- Output display data (paddle, bricks, ball)
            if hCounter >= paddle_x and hCounter < paddle_x + paddle_width and
               vCounter >= vDisplay - paddle_height and vCounter < vDisplay then
                R <= (others => '1');  -- White paddle
                G <= (others => '1');
                B <= (others => '1');
            elsif vCounter / brick_height < brick_rows and hCounter / brick_width < bricks_per_row and
                  bricks(vCounter / brick_height, hCounter / brick_width) = '1' and
                  hCounter >= (hCounter / brick_width) * brick_width and hCounter < ((hCounter / brick_width) + 1) * brick_width and
                  vCounter >= (vCounter / brick_height) * brick_height and vCounter < ((vCounter / brick_height) + 1) * brick_height then
                R <= (others => '1');  -- Red bricks
                G <= (others => '0');
                B <= (others => '0');
            elsif hCounter >= ball_x and hCounter < ball_x + ball_size and
                  vCounter >= ball_y and vCounter < ball_y + ball_size then
                R <= (others => '1');  -- White ball
                G <= (others => '1');
                B <= (others => '1');
            else
                -- Default to background color
                R <= (others => '0');
                G <= (others => '0');
                B <= (others => '0');
            end if;
        else
            BLANK <= '1';  -- Blanking period
            -- Set RGB to black during blanking
            R <= (others => '0');
            G <= (others => '0');
            B <= (others => '0');
        end if;
    end if;
end process;


end behavioral;

​

In Quartus we have this option:

https://preview.redd.it/pbkuat2apfvc1.png?width=2568&format=png&auto=webp&s=87de596f3e511e3ce711934970837ebcb4c8b124

https://preview.redd.it/belltt59pfvc1.png?width=2568&format=png&auto=webp&s=bf52f8a6728000835ed8426ae63a951e1b465430

Is there any "State Machine Viewer" option in Vivado ?

I am playing around with TerosHDL but it's to hard to use.

I'm writing a testbench.

reg [2:0] coin;

Then I wanna create a random value for this coin BUT the value only can be one of these three value: 001, 010, 100. The value will change after #10.
How can I do that ?

https://preview.redd.it/pv813ugglevc1.png?width=1920&format=png&auto=webp&s=255b366e5279b4ef783944f6563cf3b56dd54a83

I'm writing this simple testbench in Vivado. Howerver Vivado said there is an error in line 18.
But its look right to me. How can I fix that ?

As a begineer trying to learn FPGA using DE1 boards, I found it difficult to find learning materials. But came across this link recently https://fpgacademy.org/courses.html. I hope others find it useful too.

Hello everyone,

With the Altera DE2-115, the initial step involves designing the program using VHDL, followed by a simulation with ModelSim. Subsequently, the Quartus II Pin Planner is utilized to assign the device's input/output pins before downloading the design onto the Altera board. I am curious to know if the same steps apply when working with the Zynq UltraScale+ MPSoC, with the exception that Vivado is used instead of Quartus II. I would appreciate some clarification on this matter.

Thank you so much !

Hello, everyone. I'm dealing with an ethernet application for the first time and I'm trying to receive data as well as send data from my PC into my FPGA through a SFP port and send the data back out through the other SFP port which goes back into my PC(basically echo system). I first tried to create the example design and found several problems with understanding this IP

1. What protocol do I need to send from the PC(UDP, TCP, ARP, ...) and how to configure the ip as to receive which protocol.

2. For the Ethernet IP, I chose SGMII LVDS for the board interface as I want to use both SFP ports. WIll this cause any problems?

(Board: KCU105)

https://preview.redd.it/fr6z0f14rcvc1.png?width=1066&format=png&auto=webp&s=a73a7f0fbab0a680117f813ffb875c28a0a33b47

Hi everyone, I'm a newbie in CPLD.
I have the Max ii EPM240 and a 4-digit 7-segment display with two 74HC595. Could someone tell me how to display that 4-digit 7-segment in system verilog or verilog. I have displayed it in assembly and known how 74HC595 works. However, it too hard for me to display 7-segment in verilog or system verilog.
Sorry for my bad English.

I'm going to put a FSM on Basys3 board. However, I'm quite confuse with the clock signal.
First, when I write a source files, I'm not choose clock frequency, just "input clk". So that I open then xdc.files of someone on the internet: digilent-xdc/Basys-3-Master.xdc at master · Digilent/digilent-xdc (github.com)

Then I see:

## Clock signal
#set_property -dict { PACKAGE_PIN W5   IOSTANDARD LVCMOS33 } [get_ports clk]
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]

I see the W5 pin, then I search it in the Basys 3 shematic:

https://preview.redd.it/2ao9tcqpncvc1.png?width=376&format=png&auto=webp&s=14823bd43872bb512fb7e6821d345ed4ddc8d170

Oh yeah, that's W5, so maybe that pin will create 100Mhz clock and feed into "input clk" right ?
But I have some quétions:

• How can I know Duty Cycle of that 100Mhz (10ns) clock ?

• I don't understand this code: #create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5}

• What if I want the clock have 1s cycle ? How can I do that ? Does I need to write the clock divider verilog code or just simply modify this line: #create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} ?

Hi,

I wanted to clarify a point. This is about Step 5 in the design flow diagram: https://i.imgur.com/fvmDD97.jpg

For more context, you can check this post: https://www.reddit.com/r/FPGA/comments/18vq3hg/comment/kzs8smv/?utm_source=share&utm_medium=web3x&utm_name=web3xcss&utm_term=1&utm_content=share_button

In Step 5 it says "RTL vs. Gates". Is Step 5 only about Logic Equivalency Checking (LEC)? I think LEC is also called Formal Equivalency Checking which I think also comes under the umbrella of formal verification. Is it saying that at Step 5 only LEC takes place?

You can see here that Synopsys provides different apps as part of VC Formal, https://www.synopsys.com/verification/static-and-formal-verification/vc-formal.html, which can be used for formal verification. Is the formal verification done by VC Formal at Step 10? In other words, at Step 5 one is only concerned about equivalency checking and Step 10 is concerned about whole set of formal verification?